MX812 查看數據表（PDF） - MX-COM Inc
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MX812 Datasheet PDF : 13 Pages
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VSR CODEC with DRAM CONTROL
8
MX812 PRELIMINARY INFORMATION
Control Timing Information
Figure 6 shows the timing parameters for two-way communication between the µController and Cellular peripherals on the
“C-BUS.” Figure 7 shows the timing relationships between the Serial Clock and Data.
CHIP SELECT
t CSOFF
SERIAL CLOCK
t CSE
COMMAND DATA
76543210
MSB
LSB
ADDRESS/COMMAND
BYTE
REPLY DATA
Logic level is not important
t NXT
t NXT
t CK
76543210
FIRST DATA BYTE
76543210
MSB
LSB
FIRST REPLY DATA BYTE
76 54 32 10
LAST DATA BYTE
7654 32 1 0
LAST REPLY DATA BYTE
t CSH
t HIZ
Figure 6 - Control Timing Information
tCK
tCL
tCH
70% VDD
30% VDD
SERIAL CLOCK
(from C)
tCDS
tCDH
COMMAND DATA
(from C)
Figure 7 - Control Timing Relationships
REPLY DATA
(to C)
tRDS
tRDH
I bit (idle)
Device Condition
MT bit Command
Buffer Status
IF bit (Flag)
Interrupt
(IRQ) Output
New 'Store, Play or Wait'
Command from C-BUS
C1
C2
C3
Read Status Register
Command Executing
**
**
**
** The value read from the Status Register at these times will include a valid 'Power' reading if the Codec is set to the Encode mode.
C1
C2
C3
Figure 8 - Typical Command Sequences
© 1997 MX•COM Inc.
www.mxcom.com Tele: 800 638-5577 910 744-5050 Fax: 910 744-5054
Doc. # 20480076.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.
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