DS1743-85 查看數據表（PDF） - Maxim Integrated

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DS1743-85

Y2K-Compliant, Nonvolatile Timekeeping RAMs

Maxim Integrated 

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

AC TEST CONDITIONS

Output Load: 50 pF + 1TTL Gate

Input Pulse Levels: 0 to 3.0V

Timing Measurement Reference Levels:

Input: 1.5V

Output: 1.5V

Input Pulse Rise and Fall Times: 5ns

NOTES:

1) Voltages are referenced to ground.

2) Typical values are at +25°C and nominal supplies.

3) Outputs are open.

4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.

5) The CE2 control signal functions the same as the CE signal except that the logic levels for active and

inactive levels are opposite. If CE2 is used to terminate a write, the CE2 data hold time (tDH) applies.

6) Data-retention time is at +25°C.

7) Each DS1743 has a built-in switch that disconnects the lithium source until VCC is first applied by the

user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting

from the time power is first applied by the user.

8) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wave-

soldering techniques as long as temperatures as long as temperature exposure to the lithium energy

source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is

acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for

details regarding the PowerCap package.

PACKAGE INFORMATION

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,

but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE

28 EDIP (740)

34 PWRCP

PACKAGE CODE

MDF28+2

PC1+2

OUTLINE NO.

21-0245

21-0246

LAND PATTERN NO.

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