DS1743W-150IND 查看數據表（PDF） - Maxim Integrated

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DS1743W-150IND

Y2K-Compliant, Nonvolatile Timekeeping RAMs

Maxim Integrated 

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

TIME AND DATE OPERATION

The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the

RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The

contents of the time and date registers are in the BCD format. The day-of-week register increments at

midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1

equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined

operation.

CLOCK OPERATIONS-READING THE CLOCK

While the double-buffered register structure reduces the chance of reading incorrect data, internal updates

to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in

transition. However, halting the internal clock register updating process does not affect clock accuracy.

Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long

as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that

is day, date, and time that was current at the moment the halt command was issued. However, the internal

clock registers of the double-buffered system continue to update so that the clock accuracy is not affected

by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register

updating process has been re-enabled. Updating is within a second after the read bit is written to 0.

The READ bit must be a zero for a minimum of 500µs to ensure the external registers are updated.

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