DS1743WP-120IND 查看數據表（PDF） - Maxim Integrated

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DS1743WP-120IND

Y2K-Compliant, Nonvolatile Timekeeping RAMs

Maxim Integrated 

Figure 1. Block Diagram

DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs

Dallas

Semiconductor

DS1743

Table 1. Truth Table

VCC

CE CE2 OE WE

VIH X X X

X VIL X X

VCC > VPF

VIL VIH X VIL

VIL VIH VIL VIH

VIL VIH VIH VIH

VSO < VCC < VPF X

XXX

VCC<VSO<VPF

X

X XX

MODE

Deselect

Deselect

Write

Read

Read

Deselect

Deselect

DQ

High-Z

High-Z

Data In

Data Out

High-Z

High-Z

High-Z

POWER

Standby

Standby

Active

Active

Active

CMOS Standby

Data-Retention

Mode

SETTING THE CLOCK

As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates

to the DS1743 registers. The user can subsequently load correct date and time values into all eight

registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new

settings into the clock, allowing timekeeping operations to resume from the new set-point.

Again referring to Table 2, bit 6 of the Control register is the R (read) bit. Setting the R bit to 1 halts

updates to the DS1743 registers. The user can subsequently read the date and time values from the eight

registers without those contents possibly changing during those I/O operations. A subsequent write cycle

of 00h to the Control register to clear the R bit allows timekeeping operations to resume from the previous

set-point.

The pre-existing contents of the Control register bits 0:5 (Century value) are ignored/unmodified by a

write cycle to Control if either the W or R bits are being set to 1 in that write operation.

The pre-existing contents of the Control register bits 0:5 (Century value) will be modified by a write cycle

to Control if the W bit is being cleared to 0 in that write operation.

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