88E1111 查看數據表（PDF） - Unspecified
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88E1111 Datasheet PDF : 52 Pages
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Signal Description
Pin Description
The TBI interface supports 1000BASE-T mode of operation. The TBI interface uses the same pins as the GMII
interface. The MAC interface pins are 3.3V tolerant.
Table 3: TBI Interface
117-TFBGA 96-BCC
Pin #
Pin #
E2
8
128-PQFP Pin Name
Pin #
14
GTX_CLK/
TBI_TXCLK
Pin
Ty p e
I
Description
TBI Transmit Clock. In TBI mode, GTX_CLK
is used as TBI_TXCLK. TBI_TXCLK is a 125
MHz transmit clock.
TBI_TXCLK provides a 125 MHz clock refer-
ence for TX_EN, TX_ER, and TXD[7:0].
D1
4
10
TX_CLK/RCLK1 O, Z
TBI 62.5 MHz Receive Clock- even code
group. In TBI mode, TX_CLK is used as
RCLK1.
J2
20
29
TXD[7]
I
TBI Transmit Data. TXD[7:0] presents the
J1
19
28
TXD[6]
data byte to be transmitted onto the cable.
H3
18
26
TXD[5]
H1
17
25
TXD[4]
TXD[9:0] are synchronous to GTX_CLK.
H2
16
24
TXD[3]
G3
14
20
TXD[2]
Inputs TXD[7:4] should be tied low if not
G2
12
19
TXD[1]
used (e.g., RTBI mode).
F1
11
18
TXD[0]
E1
9
16
TX_EN/
I
TBI Transmit Data. In TBI mode, TX_EN is
TXD8
used as TXD8.
TXD[9:0] are synchronous to GTX_CLK.
F2
7
13
TX_ER/
I
TBI Transmit Data. In TBI mode, TX_ER is
TXD9
used as TXD9.
TXD[9:0] are synchronous to GTX_CLK.
TX_ER should be tied low if not used (e.g.,
RTBI mode).
C1
2
7
RX_CLK/
O, Z
TBI 62.5 MHz Receive Clock- odd code
RCLK0
group. In the TBI mode, RX_CLK is used
as RCLK0.
C5
86
120
RXD[7]
O, Z
TBI Receive Data code group [7:0]. In the
A2
87
121
RXD[6]
TBI mode, RXD[7:0] present the data byte to
A1
89
123
RXD[5]
be transmitted to the MAC. Symbols
C4
90
124
RXD[4]
received on the cable are decoded and pre-
B3
91
125
RXD[3]
sented on RXD[7:0].
C3
93
126
RXD[2]
D3
92
128
RXD[1]
RXD[7:0] are synchronous to RCLK0 and
B2
95
3
RXD[0]
RCLK1.
B1
94
4
RX_DV/
O, Z
TBI Receive Data code group bit 8. In the
RXD8
TBI mode, RX_DV is used as RXD8.
RXD[9:0] are synchronous to RCLK0 and
RCLK1.
Copyright © 2009 Marvell
March 4, 2009, Advance
Document Classification: Proprietary Information
Doc. No. MV-S105540-00, Rev. --
Page 15
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