ADM1066ACPZ-REEL 查看數據表（PDF） - Analog Devices
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ADM1066ACPZ-REEL Datasheet PDF : 36 Pages
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ADM1066
Data Sheet
Parameter
Conversion Time
Offset Error
Input Noise
AUX1, AUX2 Input Impedance
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x7F Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
INL
DNL
Gain Error
Maximum Load Current (Source)
Maximum Load Current (Sink)
Maximum Load Capacitance
Settling Time to 50 pF Load
Load Regulation
PSRR
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge-Pump)
Mode (PDO1 to PDO6)
Output Impedance
VOH
VOH
VOH2
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
VOL
IOL2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Three-State Output Leakage
Current
Oscillator Frequency
Min
1
0.592
0.796
0.996
1.246
2.043
1
11
10.5
8
2.4
VPU − 0.3
0
16
90
Typ
0.44
84
0.25
8
0.6
0.8
1
1.25
601.25
2.36
100
100
2.5
60
40
2.048
−0.25
0.25
60
500
12.5
12
10
20
20
100
Max
±2
0.603
0.803
1.003
1.253
±0.75
±0.4
1
50
2
2.053
14
13.5
13.5
4.5
0.50
20
60
29
2
10
110
Unit
ms
ms
LSB
LSBrms
MΩ
Bits
V
V
V
V
mV
mV
LSB
LSB
%
µA
µA
pF
µs
mV
dB
dB
V
mV
mV
µF
dB
kΩ
V
V
V
µA
V
V
V
V
mA
mA
kΩ
mA
µA
kHz
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, 16× averaging enabled
VREFIN = 2.048 V
Direct input (no attenuator)
Six DACs are individually selectable for centering on one of four
output voltage ranges
Same range, independent of center point
Endpoint corrected
Per mA
DC
100 mV step in 20 ns with 50 pF load
No load
Sourcing current, IDACxMAX = −100 µA
Sinking current, IDACxMAX = 100 µA
Capacitor required for decoupling, stability
DC
IOH = 0 µA
IOH = 1 µA
IOH = 7 µA
2 V < VOH < 7 V
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
VPU to VPx = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source current
available through any number of PDO pull-up switches
configured onto any one VPx pin
VPDO = 14.4 V
All on-chip time delays derived from this clock
Rev. F | Page 6 of 36
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