TLK3138 查看數據表（PDF） - Unspecified

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产品描述 (功能)

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TLK3138

Dual XAUI Transceiver

Unspecified 

TLK3138

www.ti.com

SLLS762A – FEBRUARY 2007 – REVISED APRIL 2007

DETAILED DESCRIPTION (continued)

In the receive datapath A FIFO, placed on the output of the serial to parallel conversion logic for each serial link,

compensates for channel skew, clock phase and frequency tolerance differences between the recovered clocks

for each serial links and the receive output clock, RX_CLK. This FIFO has a total depth of sixteen ten bit entries,

giving 30 bit time deskew (channel to channel skew) alignment capability in standard mode. See HSTL Output

Switching Characteristics (DDR) table in the Electrical Characteristics section for more details on XGMII timing.

TCLK

Source Centered (DDR)

TXD(31:0)

TXC(3:0)

tSETUP

tHOLD

Data

tSETUP

tHOLD

Data

Figure 13. Transmit Interface Timing

PARALLEL INTERFACE DATA

Data placed on the XGMII transmit input bus is latched and then phase aligned to the internal version of the

transmit reference clock, 8b/10b encoded, serialized, then transmitted sequentially beginning with the LSB of the

encoded data byte over the differential high speed serial transmit pins.

The XGMII receive data bus outputs four bytes on RXD(31:0). Control character (K-characters) reporting for

each byte is done by asserting the corresponding control pin, RXC(3:0). When RXC is asserted, the 8 bits of

data corresponding to the control pin is to be interpreted as a K-character. If an error is uncovered in decoding

the data, the control pin is asserted and 0xFE is output for the corresponding byte.

TRANSMISSION LATENCY

For each channel, the data transmission latency of the TLK3138 is defined as the delay from the rising or falling

edge of the selected transmit clock when valid data is on the transmit data pins to the serial transmission of bit

0, as shown in Figure 14. The maximum transmit latency (TLATENCY) is 650 bit times; the standard allows a

combined latency (TX + RX) of 2048 bit times.

TXxP

TXxN

TLATENCY

10 bit Code

Transmitted

TXD[0-31]

Bytes to be

Transmitted

TCLK

Figure 14. Transmission Latency

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