NT68625 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

NT68625

Flat Panel Monitor Controller

Unspecified 

NT68665/NT68625

6.8. Sync Processor

The NT68665/NT68625 has a Sync Processor block providing the capability of measuring the

horizontal and vertical timing parameters of the input video source. This information may be used to

determine the video format and to detect a change in the input timing. It is also capable of detecting

the field type of interlaced formats.

Hsync /Vsync Frequency and Polarity Detection

GI_HCNT, the 13 bits Hsync period counter counts the time of 32xHSYNC period, then loads the

result into the GI_HCNT latch. The output value will be [((REFCLK / 4 x 32)/HFreq)], updated once per

VSYNC/CVSYNC period when VSYNC/CVSYNC is present or continuously updated when

VSYNC/CVSYNC is non-present.

GI_VCNT, the 13 bits Vsync period counter counts the time between two VSYNC pulses, then loads

the result into the GI_VCNT latch. The output value will be [(REFCLK/(256 x Vfreq))], updated every

VSYNC/CVSYNC period. An extra overflow bit indicates the condition of H/V counter overflow.

The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse

duration is longer than that of the low pulse, the negative polarity is asserted; otherwise, positive

polarity is asserted. The INT_HPOL interrupt is set when the GI_HPOL value changes. The

INT_VPOL interrupt is set when the GI_VPOL value changes.

H/V Present Check

The Hsync present function checks the input HSYNCI pulse, GI_HPRE flag is set when HSYNCI is

over HSYNC Present High Counter Threshold (HPRE_THR_HI) or cleared when HSYNC is under

HSYNC Present Low Counter Threshold (HPRE_THR_LO). The Vsync present function checks the

input VSYNCI pulse, the GI_VPRE flag is set when VSYNCI is over VSYNC Present High Counter

Threshold (VPRE_THR_HI) or cleared when VSYNC is under VSYNC Present Low Counter

Threshold (VPRE_THR_LO). The INT_HPRE interrupt is set when the GI_HPRE value changes. The

INT_VPRE interrupt is set when the GI_VPRE /GI_CSPRE value change.

Timing Change Detection

The INT_VFREQ/INT_HFREQ interrupt is set when GI_VCNT / GI_HCNT value changes or overflows.

2006-02-09

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Ver. 0.40

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