DM560P 查看數據表（PDF） - Davicom Semiconductor, Inc.
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DM560P Datasheet PDF : 43 Pages
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DM560P
V.90 Integrated Data/Fax/Voice/Speakerphone Modem Device Set
Modem Control Register (MCR): Address 4
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0 0 0 0 0 0 RTS DTR
Bit 0: This bit asserts a Data Terminal Ready
condition that is readable via port P1.1 of the micro-
controller 80C32. When bit 0 is set to logic 1, the P1.1
is forced to logic 0. When bit 0 is reset to logic 0, the
P1.1 is forced to logic 1.
Bit 1: This bit asserts a Request To Send condition
that is readable via port P3.4 of the micro-controller
80C32. When bit 1 is set to logic 1, the P3.4 is forced
to logic 0. When bit 1 is reset to logic 0, the P3.4 is
forced to logic 1.
Line Status Register (LSR): Address 5
Reset State 60h, Read only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RCV ETEMT THRE BI FE PE OE DR
This register provides status information to the host
PC concerning character transfer. Bit 1-4 indicates
error conditions that produce a Receiver Line Status
interrupt whenever any of the corresponding
conditions are detected. The Line Status Register is
valid for read operations only.
Bit 0: Set to logic 1 when a received character is
available in the RxFIFO. This bit is reset to logic 0
when the RxFIFO is empty.
Bit 1: An Overrun error will occur only after the
RxFIFO is full and the next character has overwritten
the unread FIFO data. This bit is reset upon reading
the Line Status Register.
Bit 2: A logic 1 indicates that a received character
does not have the correct even or odd parity as
selected by the Parity Select bit. This error is set when
the corresponding character is at the top of the
RxFIFO. It will remain set until the CPU reads the
LSR.
Bit 3: This bit is the Framing Error (FE) indicator. Bit 3
indicates that the received character did not have a
valid stop bit. Bit 3 is set to a logic 1 whenever the stop
bit following the last data bit or parity bit is detected as
a zero bit (spacing level). The FE bit is reset whenever
the CPU reads the contents of the Line Status
Register. The FE error condition is associated with the
particular character in the FIFO to which it applies.
This error is revealed to the CPU when its associated
character is at the top of the FIFO.
Bit 4: This bit is a Break Interrupt (BI) indicator. Bit 4
is set to logic 1 whenever the received data input is
held in the Spacing (logic 0) state for longer than a full
word transmission time (that is, the total time of Start
bit + data bits + Parity + Stop bits). The BI indicator is
reset whenever the CPU reads the contents of the
Line Status Register. The BI error condition is
associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU
when its associated character is at the top of the FIFO.
Bit 5: This bit is a Transmitter Holding Register Empty
indicator. Bit 5 indicates that UART is ready to accept
a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU
when the Transmit Holding Register Empty Interrupt
Enable is set high. The THRE bit is reset to logic 0
when the host CPU loads a character into the
Transmit Holding register. In the FIFO mode, this bit is
set when the TxFIFO is empty, and is cleared when at
least 1 byte is written to the TxFIFO.
Bit 6: This bit is the Transmitter Empty indicator. Bit 6
is set to a logic 1 whenever the Transmitter Holding
Register (THR) is empty, and is reset to a logic 0
whenever the THR contains a character. In FIFO
mode, this bit is set to 1 whenever the transmit FIFO is
empty.
Bit 7: In character mode, this bit is 0. In FIFO mode,
this bit is set when there is at least one parity error,
framing error, or break indication in the FIFO. If there
are no subsequent errors in the FIFO, LSR7 is cleared
when the CPU reads the LSR.
14
Preliminary
Version: DM560P-DS-P07
August 11, 2000
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