DM336P 查看數據表（PDF） - Davicom Semiconductor, Inc.
零件编号
产品描述 (功能)
生产厂家
DM336P Datasheet PDF : 40 Pages
| |||
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
(1) Card Control Registers (continued)
Index
07H
Name
Type
Definition
Logical Device
R 00H (Only one logical device in DM6383A)
(2) Logical Device Control Registers
Index
30H
31H
Name
Activate
I/O Range Check
Type
Definition
R/W For each logical device, there is one Activate register that controls
whether or not the device is active on the ISA bus. Bit[0], if set, activates
the logical device. Before a logical device is activated, I/O range check
must be disabled.
R/W This register is used to perform a conflict check on the I/O port range
programmed for use by a logical device.
Bit[1] - This bit, when set, enables I/O range check. I/O port range check
is only valid when the logical device is inactive.
Bit[0] - If set, this bit forces logical device to respond to I/O reads within
logical device assigned I/O range with a 55H when I/O range check is in
operation. If clear, the logical device drives AAH.
c. Logical Device Configuration Registers
(1) I/O Configuration Registers
Index
60H
61H
Name
I/O base address
bits[15:8]
I/O base address
bits[7:3]
Type
Definition
R/W Read/write value indicating the selected I/O Lower Limit Address Bits
[15:8] for I/O descriptor 0. If a logical device indicates it uses only 10
bits for decoding, then bits [15:10] need not to be supported.
R/W Read/write value indicating the selected I/O Lower Input Address Bits
[7:3] for I/O descriptor 0.
(2) Interrupt Configuration Registers
Index
70H
71H
Name
IRQ level
IRQ type bits [7:0]
Type
R/W
R
Definition
Read/write value indicating a selected Interrupt Level Bits[3:0] Select
which ISA interrupt level is used. A value of 1 selects IRQ1, 15 selects
IRQ15, etc. IRQ0 is not a valid interrupt selection.
Read/write value indicating which type of interrupt is used for the IRQ
selected above Bit[1] - Level, 1 = high, 0 = low Bit[0] - Type, 1= level, 0 =
edge for DM6383A, this register is read only with value = 02H.
(3) Vender Define Register
Index
F0H
F1H
F2H
Name
Auto Configuration
IRQ Status Enable
IRQ Status
Type
R/W
W
R
Definition
The I/O base address and IRQ can be configured by CPU through this
register. (It can also be configured by micro-controller. See previous
section).
Before reading IRQ lines status, bit 0 must be set in order to load IRQ
lines status to IRQ Status register, bit 1 enable Pull Low resistor.
This register responds to IRQ lines status to determine which interrupt
has been used by PC system. bit 0: IRQ 3 bit 1: IRQ 4 bit 2: IRQ 5 bit 3:
IRQ 7 bit 4: IRQ 10 bit 5: IRQ11 bit 6: IRQ12 bit 7: IRQ15.
Final
15
Version: DM336P-DS-F02
August 15, 2000
Share Link: 