BQ4285S 查看數據表（PDF） - Unspecified

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BQ4285S

Real-Time Clock (RTC) With NVRAM Control

Unspecified 

bq4285

Block Diagram

Pin Descriptions

AD0–AD7 Multiplexed address/data input/

output

The bq4285 bus cycle consists of two

phases: the address phase and the data-

transfer phase. The address phase pre-

cedes the data-transfer phase. During the

address phase, an address placed on

AD0–AD7 is latched into the bq4285 on the

falling edge of the AS signal. During the

data-transfer phase of the bus cycle, the

AD0–AD7 pins serve as a bidirectional data

bus.

MOT

Bus type select input (PLCC package

only)

MOT selects bus timing for either Motorola

or Intel architecture. This pin should be

tied to VCC for Motorola timing or to VSS for

Intel timing (see Table 1). The setting

should not be changed during system opera-

tion. MOT is internally pulled low by a 20K

Ω resistor. For the DIP and SOIC pack-

ages, this pin is internally connected to VSS,

enabling the bus timing for the Intel archi-

tecture.

CS

Chip select input

CS should be driven low and held stable

during the data-transfer phase of a bus cy-

cle accessing the bq4285.

Table 1. Bus Setup

Bus MOT

DS

R/W

AS

Type Level Equivalent Equivalent Equivalent

Motorola VCC DS, E, or R/W

AS

Φ2

Intel

VSS RD,

MEMR,

or I/OR

WR,

MEMW,

or I/OW

ALE

Jan. 1999 D

2

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