BQ4285S 查看數據表（PDF） - Unspecified

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BQ4285S

Real-Time Clock (RTC) With NVRAM Control

Unspecified 

bq4285

AS

DS

R/W

INT

RST

Address strobe input

AS serves to demultiplex the address/data

bus. The falling edge of AS latches the ad-

dress on AD0–AD7. This demultiplexing

process is independent of the CS signal.

For DIP, SOIC, and PLCC packages with

MOT = VCC, the AS input is provided a sig-

nal similar to ALE in an Intel-based sys-

tem.

Data strobe input

For DIP, SOIC, and PLCC packages with

MOT = VSS, the DS input is provided a sig-

nal similar to RD, MEMR, or I/OR in an

Intel-based system. The falling edge on DS

is used to enable the outputs during a read

cycle.

For the PLCC package, when MOT = VCC,

DS controls data transfer during a bq4285

bus cycle. During a read cycle, the bq4285

drives the bus after the rising edge on DS.

During a write cycle, the falling edge on DS

is used to latch write data into the chip.

Read/write input

For DIP, SOIC, and PLCC packages with

MOT = VSS, R/W is provided a signal simi-

lar to WR, MEMW, or I/OW in an Intel-

based system. The rising edge on R/W

latches data into the bq4285.

For the PLCC package, when MOT = VCC,

the level on R/W identifies the direction of

data transfer. A high level on R/W indi-

cates a read bus cycle, whereas a low on

this pin indicates a write bus cycle.

Interrupt request output

INT is an open-drain output. INT is as-

serted low when any event flag is set and

the corresponding event enable bit is also

set.

INT becomes high-impedance

whenever register C is read (see the Con-

trol/Status Registers section).

Reset input

The bq4285 is reset when RST is pulled

low. When reset, INT becomes high-

impedance, and the bq4285 is not accessi-

ble. Table 4 in the Control/Status Registers

section lists the register bits that are

cleared by a reset.

SQW

BC

X1–X2

CEIN

CEOUT

VOUT

VCC

VSS

Jan. 1999 D

3

Reset may be disabled by connecting RST

to VCC. This allows the control bits to re-

tain their states through power-

down/power-up cycles.

Square-wave output

SQW may output a programmable fre-

quency square-wave signal during normal

(VCC valid) system operation. Any one of

the 13 specific frequencies may be selected

through register A. This pin is held low

when the square-wave enable bit (SQWE)

in register B is 0 (see the Control/Status

Registers section).

3V backup cell input

BC should be connected to a 3V backup cell

for RTC operation and storage register non-

volatility in the absence of power. When

VCC slews down past VBC (3V typical), the

integral control circuitry switches the

power source to BC. When VCC returns

above VBC, the power source is switched to

VCC.

Upon power-up, a voltage within the VBC

range must be present on the BC pin for

the oscillator to start up.

Crystal inputs

The X1–X2 inputs are provided for an ex-

ternal 32.768Khz quartz crystal, Daiwa

DT-26 or equivalent, with 6pF load capaci-

tance. A trimming capacitor may be neces-

sary for extremely precise time-base gen-

eration.

External RAM chip enable input,

active low

CEIN should be driven low to enable the

controlled external RAM. CEIN is internally

pulled up with a 50KΩ resistor.

External RAM chip enable output,

active low

When power is valid, CEOUT reflects CEIN.

Supply output

VOUT provides the higher of VCC or VBC,

switched internally, to supply external RAM.

+5V supply

Ground

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