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74VHC112M(2007) 查看數據表(PDF) - Fairchild Semiconductor

零件编号
产品描述 (功能)
生产厂家
74VHC112M
(Rev.:2007)
Fairchild
Fairchild Semiconductor Fairchild
74VHC112M Datasheet PDF : 9 Pages
1 2 3 4 5 6 7 8 9
AC Electrical Characteristics
Symbol
fMAX
Parameter
Maximum Clock
Frequency
tPLH, tPHL Propagation Delay Time
(CP to Qn or Qn)
tPLH, tPHL Propagation Delay Time
(PR or CLR to Qn or Qn)
CIN
Input Capacitance
CPD
Power Dissipation
Capacitance
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Conditions
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
CL = 15pF
CL = 50pF
VCC = Open
(2)
TA = 25°C
Min. Typ. Max.
110 150
90 120
150 200
120 185
8.5 11.0
10.0 15.0
5.1 7.3
6.3 10.5
6.7 10.2
9.7 13.5
4.6 6.7
6.4 9.5
4
10
18
TA = –40°C
to +85°C
Min. Max. Units
100
MHz
80
135
MHz
110
1.0 13.4 ns
1.0 16.5
1.0 8.8 ns
1.0 12.0
1.0 11.7 ns
1.0 15.0
1.0 8.0 ns
1.0 11.0
10 pF
pF
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated
by the following equation: CPD (total) = 30 + 14 • n
AC Operating Requirements
Symbol
tW
Parameter
Minimum Pulse Width
(CP or CLR or PR)
tS
tH
tREC
Minimum Setup Time
(Jn or Kn to CPn)
Minimum Hold Time
(Jn or Kn to CPn)
Minimum Recovery Time
(CLR or PR to CP)
Note:
3. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V.
VCC (V)(3)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
TA = 25°C
TA = –40°C to +85°C
Typ.
Guaranteed Minimum
5.0
5.0
5.0
5.0
5.0
5.0
4.0
4.0
1.0
1.0
1.0
1.0
6.0
6.0
5.0
5.0
Units
ns
ns
ns
ns
©1995 Fairchild Semiconductor Corporation
74VHC112 Rev. 1.2
5
www.fairchildsemi.com

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