CY7C1049CV33 查看數據表（PDF） - Cypress Semiconductor
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CY7C1049CV33 Datasheet PDF : 13 Pages
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CY7C1049CV33
Selection Guide
Maximum access time
Maximum operating current
Maximum CMOS standby current
Pin Configuration
Description
Figure 1. 44-pin TSOP II (Top View)
NC 1
NC 2
A0 3
A1 4
A2 5
A3 6
A4 7
CE 8
I/O0 9
I/O1 10
VCC 11
VSS 12
I/O2 13
I/O3 14
WE 15
A5 16
A6 17
A7 18
A8 19
A9 20
NC 21
NC 22
44 NC
43 NC
42 NC
41 A18
40 A17
39 A16
38 A15
37 OE
36 I/O7
35 I/O6
34 VSS
33 VCC
32 I/O5
31 I/O4
30 A14
29 A13
28 A12
27 A11
26 A10
25 NC
24 NC
23 NC
-8
-10
Unit
8
10
ns
100
100
mA
10
10
mA
Pin Definitions
Pin Name
A0–A18
I/O0–I/O7
NC[1]
WE
44-pin TSOP II
Pin Number
3–7, 16–20, 26–30,
38–41
9, 10, 13, 14, 31,
32, 35, 36
1, 2, 21, 22, 23, 24,
25, 42, 43, 44
15
CE
8
OE
37
VSS, GND
VCC
12, 34
11, 33
I/O Type
Input
Input/Output
No connect
Input/Control
Input/Control
Input/Control
Ground
Power supply
Description
Address inputs used to select one of the address locations.
Bidirectional data I/O lines. Used as input or output lines depending on
operation.
No connects. This pin is not connected to the die.
Write Enable input, active LOW. When selected LOW, a WRITE is
conducted. When selected HIGH, a READ is conducted.
Chip Enable input, active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
Output Enable, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins.
Ground for the device. Should be connected to ground of the system.
Power supply inputs to the device.
Note
1. NC pins are not connected on the die.
Document #: 38-05006 Rev. *M
Page 3 of 13
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