CY7C1049CV33 查看數據表（PDF） - Cypress Semiconductor
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CY7C1049CV33 Datasheet PDF : 13 Pages
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AC Switching Characteristics
Over the Operating Range
Parameter [5]
Description
Read Cycle
tpower[6]
VCC(typical) to the first access
tRC
Read cycle time
tAA
Address to data valid
tOHA
Data Hold from Address Change
tACE
CE LOW to data valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to data valid
OE LOW to Low Z[7]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
tPU
CE LOW to power up
tPD
CE HIGH to power down
Write Cycle [9, 10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE HIGH to Low Z[7]
WE LOW to High Z[7, 8]
CY7C1049CV33
-8
Min
Max
100
–
8
–
–
8
3
–
–
8
–
5
0
–
–
4
3
–
–
4
0
–
–
8
8
–
6
–
6
–
0
–
0
–
6
–
4
–
0
–
3
–
–
4
-10
Min
Max Unit
100
–
s
10
–
ns
–
10
ns
3
–
ns
–
10
ns
–
5
ns
0
–
ns
–
5
ns
3
–
ns
–
5
ns
0
–
ns
–
10
ns
10
–
ns
7
–
ns
7
–
ns
0
–
ns
0
–
ns
7
–
ns
5
–
ns
0
–
ns
3
–
ns
–
5
ns
Notes
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V.
6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed.
7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured ±500 mV from steady-state voltage.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of
these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05006 Rev. *M
Page 6 of 13
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