CY7C1049CV33 查看數據表（PDF） - Cypress Semiconductor

零件编号

产品描述 (功能)

生产厂家

CY7C1049CV33

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049CV33

Switching Waveforms

Figure 3. Read Cycle No. 1 (Address Transition Controlled) [11, 12]

tRRCC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

2

ADDRESS

CE

OE

DATA OUT

VCC

SUPPLY

CURRENT

Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13]

tRC

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Notes

11. Device is continuously selected. OE, CE = VIL.

12. WE is HIGH for read cycles.

13. Address valid before or similar to CE transition LOW.

Document #: 38-05006 Rev. *M

Page 7 of 13

[+] Feedback

Share Link: