DS5002FMN-16 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS5002FMN-16 Datasheet PDF : 25 Pages
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DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS
(VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 1 and Figure 2)
#
PARAMETER
SYMBOL
CONDITIONS
1 Oscillator Frequency
2 ALE Pulse Width
3 Address Valid to ALE Low
4 Address Hold After ALE Low
14 RD Pulse Width
15 WR Pulse Width
1 / tCLK
tALPW
tAVALL
tAVAAV
tRDPW
tWRPW
16 RD Low to Valid Data In
tRDLDV
12MHz
16MHz
17 Data Hold after RD High
18 Data Float after RD High
19 ALE Low to Valid Data In
tRDHDV
tRDHDZ
tALLVD
12MHz
16MHz
20 Valid Address to Valid Data In
tAVDV
12MHz
16MHz
21 ALE Low to RD or WR Low
22
Address Valid to RD or WR
Low
tALLRDL
tAVRDL
23 Data Valid to WR Going Low
tDVWRL
24 Data Valid to WR High
tDVWRH
12MHz
16MHz
25 Data Valid after WR High
26 RD Low to Address Float
27 RD or WR High to ALE High
tWRHDV
tRDLAZ
tRDHALH
MIN
1.0
2tCLK - 40
tCLK - 40
tCLK - 35
6tCLK - 100
6tCLK - 100
0
3tCLK - 50
4tCLK - 130
tCLK - 60
7tCLK - 150
7tCLK - 90
tCLK-50
tCLK - 40
MAX
16
5tCLK - 165
5tCLK - 105
2tCLK - 70
8tCLK - 150
8tCLK - 90
9tCLK - 165
9tCLK - 105
3tCLK + 50
0
tCLK + 50
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1. Expanded Data Memory Read Cycle
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