GT28F160S3-130 查看數據表（PDF） - Intel

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GT28F160S3-130

WORD-WIDE FlashFile™ MEMORY FAMILY

Intel 

28F160S3, 28F320S3

3.0 BUS OPERATION

The local CPU reads and writes flash memory in-

system. All bus cycles to or from the flash

memory conform to standard microprocessor bus

cycles.

3.1 Read

Block information, query information, identifier

codes and Status Registers can be read

independent of the VPP voltage.

The first task is to place the device into the

desired read mode by writing the appropriate

read-mode command (Read Array, Query, Read

Identifier Codes, or Read Status Register) to the

CUI. Upon initial device power-up or after exit

from deep power-down mode, the device

automatically resets to read array mode. Control

pins dictate the data flow in and out of the

component. CE0#, CE1# and OE# must be driven

active to obtain data at the outputs. CE0# and

CE1# are the device selection controls, and,

when both are active, enable the selected

memory device. OE# is the data output (DQ0–

DQ15) control: When active it drives the selected

memory data onto the I/O bus. WE# must be at

VIH and RP# must be at VIH. Figure 17 illustrates

a read cycle.

3.2 Output Disable

With OE# at a logic-high level (VIH), the device

outputs are disabled. Output pins DQ0–DQ15 are

placed in a high-impedance state.

3.3 Standby

CE0# or CE1# at a logic-high level (VIH) places

the device in standby mode, substantially

reducing device power consumption. DQ0–DQ15

(or DQ0– DQ7 in x8 mode) outputs are placed in

a high-impedance state independent of OE#. If

deselected during block erase, programming, or

lock-bit configuration, the device continues

functioning and consuming active power until the

operation completes.

E

3.4 Deep Power-Down

RP# at VIL initiates the deep power-down mode.

In read mode, RP#-low deselects the memory,

places output drivers in a high-impedance state,

and turns off all internal circuits. RP# must be

held low for time tPLPH. Time tPHQV is required

after return from power-down until initial memory

access outputs are valid. After this wake-up

interval, normal operation is restored. The CUI

resets to read array mode, and the Status

Register is set to 80H.

During block erase, programming, or lock-bit

configuration modes, RP#-low will abort the

operation. STS in RY/BY# mode remains low

until the reset operation is complete. Memory

contents being altered are no longer valid; the

data may be partially corrupted after

programming or partially altered after an erase or

lock-bit configuration. Time tPHWL is required after

RP# goes to logic-high (VIH) before another

command can be written.

It is important in any automated system to assert

RP# during system reset. When the system

comes out of reset, it expects to read from the

flash memory. Automated flash memories

provide status information when accessed during

block erase, programming, or lock-bit

configuration modes. If a CPU reset occurs with

no flash memory reset, proper CPU initialization

may not occur because the flash memory may be

providing status information instead of array data.

Intel’s Flash memories allow proper CPU

initialization following a system reset through the

use of the RP# input. In this application, RP# is

controlled by the same RESET# signal that

resets the system CPU.

3.5 Read Query Operation

The read query operation outputs block status,

Common Flash Interface (CFI) ID string, system

interface, device geometry, and Intel-specific

extended query information.

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ADVANCE INFORMATION

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