TTB28F400B5-B80 查看數據表（PDF） - Intel

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TTB28F400B5-B80

SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT

Intel 

SMART 5 BOOT BLOCK MEMORY FAMILY

E

DEVICE

UNDER

TEST

VCC

R1

CL

R2

OUT

NOTE:

CL includes jig capacitance.

Figure 13. Test Configuration

0599-12

Test Configuration Component Values

Test Configuration

5 V Standard Test

CL (pF) R1 (Ω) R2 (Ω)

100 580 390

5 V High-Speed Test

30

580 390

RP# (P) VIH

VIL

t PLPH

(A) Reset during Read Mode

tttPPPHHHQWELVL

RP# (P) VIH

Abort

Complete

t PLRH

t PHQV

t PHWL

t PHEL

VIL

t PLPH

(B) Reset during Program or Block Erase, t PLPH < t PLRH

RP# (P) VIH

VIL

Abort Deep

Complete Power-

t PLRH

Down

t PHQV

t PHWL

t PHEL

t PLPH

(C) Reset Program or Block Erase, t PLPH > t PLRH

0599-13

Figure 14. AC Waveform for Reset Operation

Table 9. Reset Specifications(1)

Sym

Parameter

Min Max Unit

tPLPH RP# Pulse Low

60

ns

Time

tPLRH RP# Low to Reset

during Prog/Erase

12 µs

1. If RP# is tied to VCC, these specs are not applicable.

2. These specifications are valid for all product versions

(packages and speeds).

3. If RP# is asserted while a program or block erase, is

not executing, the reset will complete within tPLPH.

4. A reset time, tPHQV, is required after tPLRH until outputs

are valid. See Section 3.1.5 for detailed information.

30

ADVANCE INFORMATION

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