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TTB28F400B5-B70 查看數據表(PDF) - Intel

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TTB28F400B5-B70 Datasheet PDF : 38 Pages
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E
SMART 5 BOOT BLOCK MEMORY FAMILY
5.7 AC Characteristics—Write Operations—Commercial and Extended
Temperature
Comm Extended
#
Sym
Parameter
Note Min Max Min Max Unit
W1 tPHWL (tPHEL)
RP# High Recovery to WE# (CE#) Going
Low
450
450
ns
W2 tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Going
Low
0
0
ns
W3 tWP
Write Pulse Width
9 50
60
ns
W4 tDVWH (tDVEH) Data Setup to WE# (CE#) Going High
4 50
60
ns
W5 tAVWH (tAVEH)
Address Setup to WE# (CE#) Going High
3 50
60
ns
W6 tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High
0
0
ns
W7 tWHDX (tEHDX) Data Hold from WE# (CE#) High
40
0
ns
W8 tWHAX (tEHAX)
Address Hold from WE# (CE#) High
30
0
ns
W9 tWPH
Write Pulse Width High VCC = 5 V ± 5%
10
10
ns
VCC = 5 V ±
10%
20
20
ns
W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CE#) Going High 6,8 100
100
ns
W11 tVPWH (tVPEH)
VPP Setup to WE# (CE#) Going High
5,8 100
100
ns
W12 tQVPH
RP# VHH Hold from Valid SRD
6,8 0
0
ns
W13 tQVVL
VPP Hold from Valid SRD
5,8 0
0
ns
W14 tPHBR
Boot Block Lock Delay
7,8
100
100 ns
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer toAC
Characteristics—Read-Only Operations.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify operations.
3. Refer to command definition table for valid AIN. (Table 6)
4. Refer to command definition table for valid DIN. (Table 6)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at VHH or WP# should be held at VIH until operation completes
successfully.
7. Time tPHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
10. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first)to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
ADVANCE INFORMATION
33

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