GLT41316-70FA 查看數據表（PDF） - G-Link Technology

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GLT41316-70FA

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

G-Link Technology  

G-LINK

GLT41316

64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

June 1998 (Rev 2)

Notes

1. An initial pause of 100µs is required after power-up followed by any 8 RAS only Refresh or CAS

before RAS Refresh cycles to initialize the internal circuit.

2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times

are measured between VIH(min.) and VIL(max.), AC measurements assume tT = 3ns.

3. Measured with an equivalent to 2 TTL loads and 100pF.

4. For read cycles, the access time is defined as follows:

Input Conditions

tRAD ≤ tRAD(MAX.) and tRCD ≤ tRCD(MAX.)

tRAD(max.)< tRAD and tRCD ≤ tRCD(MAX.)

tRCD(max.)< tRCD

Access Time

tRAC(MAX.)

tAA(MAX.)

tCAC(MAX.)

tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of

operation.

5. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data

sheet

as electric characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and the data output

will remain high impedance for the duration of the cycle. If tCWD ≥ tCWD(min.),tRWD ≥ tRWD (min.) and

tAWD ≥ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data

read from the selected address. If neither of the above conditions is satisfied, the condition of the

data

out is indeterminate.

6. tAR, tWCR, and tDHR are referenced to tRAD(max.).

7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are

not referenced to VOH or VOL.

8. tCRP(min) requirement should be applicable for RAS , CAS cycle preceded by any cycles.

9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle.

10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH(min.)

should be satisfied.

11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in

late write or read modify write cycles.

G-Link Technology Corporation

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Santa Clara, CA 95051, U.S.A.

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G-Link Technology Corporation, Taiwan

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Hsin Chu, Taiwan, R.O.C.

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