HDD16M64D8W 查看數據表（PDF） - Hanbit Electronics Co.,Ltd
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HDD16M64D8W
Hanbit Electronics Co.,Ltd
HDD16M64D8W Datasheet PDF : 10 Pages
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HANBit
HDD16M64D8W
Clock high level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK
tDQSCK
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Output data access time from CK/CK
tAC
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.6
-
+0.5
-
+0.5 ns
Read Preamble
tRPRE
0.9 1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4 0.6
0.4
0.6
0.4
0.6
tCK
Data out high impedence time from CK-/CK
tHZQ
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
2
CK to valid DQS-in
tDQSS
0.75 1.25 0.75 1.25 0.75 1.25 tCK
DQS-in setup time
tWPRES
0
0
0
ns
3
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
DQS-in falling edge to CK rising-setup time
tDSS
0.2
0.2
0.2
tCK
DQS-in falling edge to CK rising hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9 1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time
tIS
1.1
0.9
0.9
ns
Address and Control Input hold time
tIH
1.1
0.9
0.9
ns
Mode register set cycle time
tMRD
16
15
15
ns
DQ & DM setup time to DQS
tDS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
tDH
0.6
0.5
0.5
ns
DQ & DM input pulse width
tDIPW
2
1.75
1.75
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
116
95
ns
Exit self refresh to bank active command
tXSA
80
75
75
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
tREF
15.6
15.6
15.6
us
1
Output DQS valid window
tQH
0.35
0.35
0.35
tCK
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
4
Notes :
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to
crosstalk (tJIT(crosstalk) ) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
Δ tIS
(V/ns)
(ps)
0.5
0
0.4
+50
0.3
+100
Δ tIH
(ps)
0
+50
+100
URL : www.hbe.co.kr
REV 2.0 (November.2002)
7
HANBit Electronics Co.,Ltd.
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