HDMP-0452 查看數據表（PDF） - HP => Agilent Technologies

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HDMP-0452

Quad Port Bypass Circuit with CDR for Fibre Channel Arbitrated Loops

HP => Agilent Technologies 

GND

VCC

FM_NODE [1]–

FM_NODE [1]+

VCCHS[1]

TO_NODE [1]–

TO_NODE [1]+

GND

FM_NODE [0]–

FM_NODE [0]+

GND

44 43 42 41 40 39 38 37 36 35 34

1

33

2

32

3

31

4

Agilent

30

5

29

6

HDMP-0452

28

7

nnnn-nnn Rz.zz

27

S YYWW

8

26

9

25

10

24

11

23

12 13 14 15 16 17 18 19 20 21 22

GND

VCCA

TO_NODE[4]+

TO_NODE[4]–

VCCHS[4]

FM_NODE[4]+

FM_NODE[4]–

VCCHS[0]

TO_NODE[0]–

TO_NODE[0]+

GND

nnnn-nnn = WAFER LOT – BUILD NUMBER

Rz.zz = DIE REVISION

S = SUPPLIER CODE

YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)

COUNTRY = COUNTRY OF MANUFACTURE

(ON BACK SIDE)

Figure 2. HDMP-0452 package layout and marking, top view.

I/O Type Definitions

I/O Type

I-LVTTL

O-LVTTL

HS_OUT

HS_IN

C

S

Definition

LVTTL Input

LVTTL Output

High-Speed Output, LVPECL Compatible

High-Speed Input

External Circuit Node

Power Supply or Ground

4

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