IMC002FLSA-ET15 查看數據表（PDF） - Intel

零件编号

产品描述 (功能)

生产厂家

IMC002FLSA-ET15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

PRINCIPLES OF DEVICE OPERATION

Individual 28F008SA devices include a Command

User Interface (CUI) and a Write State Machine

(WSM) to manage write and erase functions in each

device block

The CUI serves as the device’s interface to the Card

Control Logic by directing commands to the appro-

priate device circuitry (Table 4) It allows for fixed

power supplies during block erasure and data writes

The CUI handles the WE interface into the device

data and address latches as well as system soft-

ware requests for status while the WSM is operating

The CUI itself does not occupy an addressable

memory location The CUI provides a latch used to

store the command and address and data informa-

tion needed to execute the command Erase Setup

and Erase Confirm commands require both appropri-

ate command data and an address within the block

to be erased The Data Write Setup command re-

quires both appropriate command data and the ad-

dress of the location to be written while the Data

Write command consists of the data to be written

and the address of the location to be written

The CUI initiates flash memory writing and erasing

operations only when VPP is at 12V Depending on

the application the system designer may choose to

make the VPP power supply switchable (available

when writes and erases are required) or hardwired to

VPPH When VPP e VPPL power savings are in-

curred and memory contents cannot be altered The

CUI architecture provides protection from unwanted

write and erase operations even when high voltage

is applied to VPP Additionally all functions are dis-

abled whenever VCC is below the write lockout volt-

age VLKO or when the card’s Deep-Sleep modes

are enabled The WSM automates the writing and

erasure of blocks within a device This on-chip state

machine controls block erase and data-write freeing

the host processor for other tasks After receiving

the Erase Setup and Erase Confirm commands from

the CUI the WSM controls block-erase Progress is

monitored via the device’s status register the card’s

control logic and the RDY BSY pin of the

PCMCIA interface Data-write is similarly controlled

after destination address and expected data are

supplied

Table 4 Device Command Set

28F008SA Command(1)

Bus

First Bus Ccyle

Second Bus Cycle

Cycles

Data

Data

Req’d

Operation Addr(2)

Operation Addr(2)

x8 Mode x16 Mode

x8 Mode x16 Mode

Read Array Reset

1

Intelligent Identifer

3

Read Device Status Register 2

Write

Write

Write

DA

FFH FFFFH

DA

90H 9090H

Read

DA

70H 7070H

Read

IA

IID(3)

IID(3)

DA SRD(4) SRD(4)

Clear Device Status Register 1

Write

DA

50H 5050H

Erase Setup Erase Confirm

2

Write

BA

20H

2020H

Write

BA

D0H D0D0H

Erase Suspend

Erase Resume

Write Setup Write

2

Write

DA

B0H B0B0H Write

DA

D0H D0D0H

2

Write

WA

40H 4040H

Write

WA WD(5) WD(5)

Alternate Write Setup Write(6) 2

Write

WA

10H 1010H

Write

WA WD(5) WD(5)

NOTES

1 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

2 DA e A device-level (or device pair) address within the card

BA e Address within the block of a specific device (device pair) being erased

WA e Address of memory location to be written

IA e A device-level address 00H for manufacturer code 01 for device code

3 Following the intelligent identifier command two read operations access manufacturer (89H) and device codes (A2H)

4 SRD e Data read from Device Status Register

5 WD e Data to be written at location WA Data is latched on the rising edge of WE

6 Either 40H or 10H are recognized by the WSM as the Write Setup command

16

Share Link: