IMC004FLSA-ET15 查看數據表（PDF） - Intel

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IMC004FLSA-ET15

SERIES 2 FLASH MEMORY CARDS

Intel 

SERIES 2 FLASH MEMORY CARDS

Bus

Operation

Command

x8 Mode

Write

Erase

Setup

Data e 20H

Address e Block

Within Card to be

Erased

x16 Mode

Data e 2020H

Address e Block Pair

Within Card to be

Erased

Write

Read

Erase

Data e D0H

Address e Block

Within Card to be

Erased

Defaults to Status Register

Device Sta- Data Toggle OE

tus Register CE1 or CE2 to

Read Mode update Status

Register

Data e D0D0H

Address e Block

Pair Within Card to

be Erased

Status Register

Data Toggle OE or

(CE1 and CE2 )

to update Status

Register

Standby

Check SR Bit 7

1 e Ready

0 e Busy

Check SR Bits 7 and 15

1 e Ready

0 e Busy

290434 – 19

FULL STATUS CHECK PROCEDURE

Bus

Operation

Command

x8 Mode

x16 Mode

Standby

Check SR Bit 3

1 e VPP Detected

Low

Check SR Bits

3 and 11

Either Bit 1 e VPP

Detected Low

Standby

Check SR Bits 4 and 5 Check SR Bits 4 5

Both 1 e Command

12 13

Sequence Error All 1 e Command

Sequence Error

Standby

Check SR Bit 5

1 e Block Erase

Error

Check SR Bits

5 and 13

Both 1 e Block

Erase Failure

290434 – 20

Figure 14 Device-Level Automated Erase Algorithm

NOTES

1 Repeat for subsequent data writes

2 In addition the card’s READY-BUSY STATUS REGISTER or the RDY BSY pin may be used

3 Full device-level status check can be done after each block erase or after a sequence of block erases

4 Write FFH (or FFFFH) after the last block erase operation to reset the device(s) to Ready Array Mode

5 If a block erase operation fails due to a low VPP (setting SR Bit 3) the Clear Status Register command MUST be issued

before further attempts are allowed by the Write State Machine

6 If a block erase operation fails during a multiple block erase sequence SR Bit 4 (Write Status) will not be cleared until the

Command User Interface receives the Clear Status Register command

21

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