MAX1280 查看數據表（PDF） - Maxim Integrated

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MAX1280

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference

Maxim Integrated 

400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,

Serial 12-Bit ADCs with Internal Reference

Detailed Description

The MAX1280/MAX1281 analog-to-digital converters

(ADCs) use a successive-approximation conversion tech-

nique and input track/hold (T/H) circuitry to convert an

analog signal to a 12-bit digital output. A flexible serial

interface provides easy interface to microprocessors

(µPs). Figure 3 shows a functional diagram of the

MAX1280/MAX1281.

Pseudo-Differential Input

The equivalent input circuit of Figure 4 shows the

MAX1280/MAX1281’s input architecture, which is com-

posed of a T/H, input multiplexer, input comparator,

switched-capacitor DAC, and reference.

In single-ended mode, the positive input (IN+) is con-

nected to the selected input channel and the negative

input (IN-) is set to COM. In differential mode, IN+ and

IN- are selected from the following pairs: CH0/CH1,

CH2/CH3, CH4/CH5, and CH6/CH7. Configure the

channels according to Tables 2 and 3.

The MAX1280/MAX1281 input configuration is pseudo-

differential in that only the signal at IN+ is sampled. The

return side (IN-) is connected to the sampling capacitor

while converting and must remain stable within ±0.5LSB

(±0.1LSB for best results) with respect to GND during a

conversion.

If a varying signal is applied to the selected IN-, its ampli-

tude and frequency must be limited to maintain accuracy.

The following equations determine the relationship

between the maximum signal amplitude and its frequency

in order to maintain ±0.5LSB accuracy. Assuming a sinu-

soidal signal at IN-, the input voltage is determined by:

( ) νIN- = VIN- sin(2πft)

The maximum voltage variation is determined by:

( ) max dνIN-

dt

=

VIN-

2πf ≤

1LSB

t CONV

=

VREF

212 tCONV

A 650mVp-p 60Hz signal at IN- will generate ±0.5LSB

of error when using a +2.5V reference voltage and a

2.5µs conversion time (15/fSCLK). When a DC reference

voltage is used at IN-, connect a 0.1µF capacitor to

GND to minimize noise at the input.

During the acquisition interval, the channel selected as

the positive input (IN+) charges capacitor CHOLD. The

acquisition interval spans three SCLK cycles and ends

on the falling SCLK edge after the last bit of the input

control word has been entered. At the end of the acqui-

sition interval, the T/H switch opens, retaining charge

on CHOLD as a sample of the signal at IN+. The conver-

sion interval begins with the input multiplexer switching

CHOLD from IN+ to IN-. This unbalances node ZERO at

the comparator’s input. The capacitive DAC adjusts

during the remainder of the conversion cycle to restore

node ZERO to VDD1/2 within the limits of 12-bit

resolution. This action is equivalent to transferring a

12pF x (VIN+ - VIN-) charge from CHOLD to the binary-

weighted capacitive DAC, which in turn forms a digital

representation of the analog input signal.

CS 17

SCLK 18

DIN 16

SHDN 10

INPUT

SHIFT

REGISTER

CONTROL

LOGIC

INT

CLOCK

CH0 1

CH1 2

CH2 3

CH3 4

CH4 5

CH5 6

CH6 7

CH7 8

COM 9

REFADJ 12

REF 11

OUTPUT 14 DOUT

SHIFT

REGISTER

15

SSTRB

ANALOG

INPUT

MUX

T/H

CLOCK

IN 12-BIT

SAR

ADC OUT

REF

20 VDD1

+1.22V

REFERENCE

A ≈ 2.05*

17k

19 VDD2

13 GND

+2.500V

MAX1280

MAX1281

Figure 3. Functional Diagram

GND

CAPACITATIVE

REF

DAC

INPUT

CH0

MUX

CH1

CHOLD

12pF

ZERO

COMPARATOR

CH2

CH3

CSWITCH*

CH4

6pF

CH5

HOLD

RIN

800Ω

CH6

CH7

TRACK AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES FROM

CH8

THE SELECTED IN+ CHANNEL TO

THE SELECTED IN- CHANNEL.

VDD1/2

SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.

PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM

PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.

*INCLUDES ALL INPUT PARASITICS

Figure 4. Equivalent Input Circuit

______________________________________________________________________________________ 11

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