MAX12555ETL 查看數據表（PDF） - Maxim Integrated

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MAX12555ETL

14-Bit, 95Msps, 3.3V ADC

Maxim Integrated 

14-Bit, 95Msps, 3.3V ADC

(VREFP - VREFN) x 2/3

(VREFN - VREFP) x 2/3

CLKN

CLKP

DAV

D0–D11

DOR

DIFFERENTIAL ANALOG INPUT (INP–INN)

N+4 N+5

N+3

N - 3 N - 2 N - 1 N N + 1 N +2

N+6

N+7

N+9

N+8

tAD

tDAV

tCL

tCH

tSETUP

tHOLD

N-3 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9

8.0 CLOCK-CYCLE DATA LATENCY

tSETUP

tHOLD

Figure 6. System Timing Diagram

System-Timing Requirements

Figure 6 shows the relationship between the clock, ana-

log inputs, DAV indicator, DOR indicator, and the result-

ing output data. The analog input is sampled on the

falling edge of the clock signal and the resulting data

appears at the digital outputs 8.0 clock cycles later.

The DAV indicator is synchronized with the digital out-

put and optimized for use in latching data into digital

back-end circuitry. Alternatively, digital back-end cir-

cuitry can be latched with the rising edge of the con-

version clock (CLKP-CLKN).

Data-Valid Output (DAV)

DAV is a single-ended version of the input clock (CLKP)

with a delay (tDAV). Output data changes on the falling

edge of DAV, and DAV rises once output data is valid

(Figure 6).

The state of the duty-cycle equalizer input (DCE)

changes the waveform at DAV. With the duty-cycle

equalizer disabled (DCE = low), the DAV signal is a sin-

gle-ended version of CLKP delayed by 5.2ns (tDAV).

With the duty-cycle equalizer enabled (DCE = high), the

DAV signal has a fixed pulse width that is independent of

CLKP. In either case, with DCE high or low, output data

at D13–D0 and DOR are valid from 5.5ns before the ris-

ing edge of DAV to 4.0ns after the rising edge of DAV,

and the falling edge of DAV is synchronized to have a

5.2ns (tDAV) delay from the falling edge of CLKP.

DAV is high impedance when the MAX12555 is in

power-down (PD = high). DAV is capable of sinking

and sourcing 600µA and has three times the drive

strength of D13–D0 and DOR. DAV is typically used to

latch the MAX12555 output data into an external back-

end digital circuit.

Keep the capacitive load on DAV as low as possible

(<25pF) to avoid large digital currents feeding back

into the analog portion of the MAX12555 and degrading

its dynamic performance. An external buffer on DAV

isolates it from heavy capacitive loads. Refer to the

MAX12555 evaluation kit schematic for an example of

DAV driving back-end digital circuitry through an exter-

nal buffer.

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