MAX1452 查看數據表（PDF） - Maxim Integrated

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MAX1452

Low-Cost Precision Sensor Signal Conditioner

Maxim Integrated 

MAX1452

Low-Cost Precision Sensor

Signal Conditioner

DRIVEN BY TESTER

THREE-STATE

NEED WEAK

PULLUP

DRIVEN BY MAX1452

THREE-STATE

NEED WEAK

PULLUP

DIO 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1

Figure 5. DIO Output Data Format

3) Write the load internal calibration register (LdICR) com-

mand to CRIL[3:0].

When a LdICR command is issued to the CRIL register,

the calibration register loaded depends on the address in

the internal calibration register address (ICRA). Table 12

specifies which calibration register is decoded.

Erasing and Writing the EEPROM

The internal EEPROM needs to be erased (bytes set

to FFhex) prior to programming the desired contents.

Remember to save the 3 MSBs of byte 161 hex (high byte

of the configuration register) and restore it when program-

ming its contents to prevent modification of the trimmed

oscillator frequency.

The internal EEPROM can be entirely erased with the

ERASE command, or partially erased with the PageErase

command (see Table 11, CRIL command). It is necessary

to wait 6ms after issuing the ERASE or PageErase com-

mand.

After the EEPROM bytes have been erased (value of

every byte = FFhex), the user can program its contents,

following the procedure below:

1) Write the 8 data bits to DHR[7:0] using two byte

accesses into the interface register set.

2) Write the address of the target internal EEPROM loca-

tion to IEEA[9:0] using three byte accesses into the

interface register set.

3) Write the EEPROM write command (EEPW) to

CRIL[3:0].

Serial Digital Output

When a RdIRS command is written to CRIL[3:0], DIO

is configured as a digital output and the contents of the

register designated by IRSP[3:0] are sent out as a byte

framed by a start bit and a stop bit.

Once the tester finishes sending the RdIRS command,

it must three-state its connection to DIO to allow the

MAX1452 to drive the DIO line. The MAX1452 three-

states DIO high for 1 byte time and then drive with the

start bit in the next bit period followed by the data byte and

stop bit. The sequence is shown in Figure 5.

The data returned on a RdIRS command depends on the

address in IRSP. Table 13 defines what is returned for the

various addresses.

Multiplexed Analog Output

When a RdAlg command is written to CRIL[3:0] the ana-

log signal designated by ALOC[3:0] is asserted on the

OUT pin. The duration of the analog signal is determined

by ATIM[3:0] after which the pin reverts to three-state.

While the analog signal is asserted in the OUT pin, DIO

is simultaneously three-stated, enabling a parallel wiring

of DIO and OUT. When DIO and OUT are connected in

parallel, the host computer or calibration system must

three-state its connection to DIO after asserting the stop

bit. Do not load the OUT line when reading internal

signals, such as BDR, FSOTC...etc.

The analog output sequence with DIO and OUT is shown

in Figure 6.

The duration of the analog signal is controlled by ATIM[3:0]

as given in Table 14.

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