MAX17000A(2008_10) 查看數據表（PDF） - Maxim Integrated
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MAX17000A Datasheet PDF : 31 Pages
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Complete DDR2 and DDR3 Memory
Power-Management Solution
KELVIN SENSE VIAS
UNDER THE INDUCTOR
(SEE EVALUATION KIT)
CSL
RNTC
CSH
R2
CEQ
R1
POWER STAGE LAYOUT (TOP SIDE OF PCB)
INDUCTOR
L1
OUTPUT
POWER
GROUND
KELVIN-SENSE VIAS TO
INDUCTOR PAD
INDUCTOR DCR SENSING
INPUT
SMPS
CONNECT THE
EXPOSED PAD TO
ANALOG GROUND
VTTI BYPASS
CAPACITOR
VTT BYPASS
CAPACITOR
CONNECT AGND AND PGND1 TO
THE CONTROLLER AT THE
EXPOSED PAD
VDD BYPASS
CAPACITOR
X-RAY VIEW.
IC MOUNTED
ON BOTTOM
SIDE OF PCB.
VIA TO POWER GROUND
VCC BYPASS
CAPACITOR
IC LAYOUT
Figure 9. PCB Layout Example
Chip Information
TRANSISTOR COUNT: 7856
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 TQFN
T2444-4
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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