MAX17035(2009) 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

MAX17035
(Rev.:2009)

High-Frequency, Low-Cost SMBus Chargers

Maxim Integrated 

High-Frequency,

Low-Cost SMBus Chargers

The high-side driver (DHI) swings from LX to 5V above LX

(BST) and has a typical impedance of 1.5I sourcing and

0.8I sinking. The low-side driver (DLO) swings from DLOV

to ground and has a typical impedance of 3I sinking and

3I sourcing. This helps prevent DLO from being pulled

up when the high-side switch turns on due to capacitive

coupling from the drain to the gate of the low-side MOSFET.

This places some restrictions on the MOSFETs that can be

used. Using a low-side MOSFET with smaller gate-to-drain

capacitance can prevent these problems.

Design Procedure

MOSFET Selection

Choose the n-channel MOSFETs according to the maxi-

mum required charge current. Low-current applications

usually require less attention. The high-side MOSFET

(N1) must be able to dissipate the resistive losses plus

the switching losses at both VDCI;MIN) and VDCIN(MAX).

Calculate both these sums.

Ideally, the losses at VDCIN(MIN) should be roughly equal

to losses at VDCIN(MAX) with lower losses in between. If

the losses at VDCIN(MIN) are significantly higher than the

losses at VDCIN(MAX), consider increasing the size of M1.

Conversely, if the losses at VDCIN(MAX) are significantly

higher than the losses at VIN(MIN), consider reducing the

size of M1. If DCIN does not vary over a wide range, the

minimum power dissipation occurs where the resistive

losses equal the switching losses. Choose a low-side

MOSFET that has the lowest possible on-resistance

(RDS(ON)), comes in a moderate-sized package (i.e., one

or two 8-pin SO, DPAK, or D2 PAK), and is reasonably

priced. Make sure that the DLO gate driver can supply

sufficient current to support the gate charge and the

current injected into the parasitic gate-to-drain capacitor

caused by the high-side MOSFET turning on; otherwise,

cross-conduction problems can occur. Select devices

that have short turn-off times, and make sure that:

N2(tDOFF(MAX)) - N1(tDON(MIN)) < 40ns, and

N1(tDOFF(MAX)) - N2(tDON(MIN)) < 40ns

Failure to do so could result in efficiency-reducing shoot-

through currents.

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty factor

extremes. For the high-side MOSFET, the worst-case

power dissipation (PD) due to resistance occurs at the

minimum supply voltage:

PD(High

-

Side)

=







VBATT

VDCIN





ILOAD

2





2

×

R DS(ON)

Generally, a small high-side MOSFET is desired to

reduce switching losses at high input voltages. However,

the RDS(ON) required to stay within package power-

dissipation limits often limits how small the MOSFET can

be. The optimum occurs when the switching (AC) losses

equal the conduction (RDS(ON)) losses. Switching losses

in the high-side MOSFET can become an insidious

heat problem when maximum AC adapter voltages are

applied, due to the squared term in the CV2 f switching-

loss equation. If the high-side MOSFET that was chosen

for adequate RDS(ON) at low supply voltages becomes

extraordinarily hot when subjected to VIN(MAX), then

choose a MOSFET with lower losses. Calculating the

power dissipation in M1 due to switching losses is

difficult since it must allow for difficult quantifying factors

that influence the turn-on and turn-off times. These

factors include the internal gate resistance, gate charge,

threshold voltage, source inductance, and PCB layout

characteristics. The following switching-loss calculation

provides only a very rough estimate and is no substitute

for breadboard evaluation, preferably including a

verification using a thermocouple mounted on N1:

PD(HS_Switching) = VDCIN(MAX) 2 × CRSS × fSW × ILOAD

2 × IGATE

where CRSS is the reverse transfer capacitance of N1

and IGATE is the peak gate-drive source/sink current

(3.3A sourcing and 5A sinking).

For the low-side MOSFET (N2), the worst-case power

dissipation always occurs at maximum input voltage:

PD(Low

-

Side)

=



1-









VBATT

VDCIN





ILOAD

2

2



×

R DS(ON)

Inductor Selection

The charge current, ripple, and operating frequency

(off-time) determine the inductor characteristics. For

optimum efficiency, choose the inductance according to

the following equation:

L = VBATT O tOFF/(0.3 x ICHG)

This sets the ripple current to 1/3 the charge current and

results in a good balance between inductor size and

efficiency. Higher inductor values decrease the ripple

current. Smaller inductor values require high saturation

current capabilities and degrade efficiency.

Inductor L1 must have a saturation current rating of at

least the maximum charge current plus 1/2 the ripple

current (DIL):

ISAT = ICHG + (1/2) DIL

______________________________________________________________________________________   25

Share Link: