MAX17435 查看數據表（PDF） - Maxim Integrated

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MAX17435

High-Frequency, Low-Cost SMBus Chargers

Maxim Integrated 

High-Frequency,

Low-Cost SMBus Chargers

Inductor L1 must have a saturation current rating of at

least the maximum charge current plus 1/2 the ripple

current (DIL):

ISAT = ICHG + (1/2) DIL

The ripple current is determined by:

DIL = VBATT O tOFF/L

where:

tOFF = 2.5Fs (VDCIN - VBATT)/

VDCIN for VBATT < 0.88 VDCIN

or:

tOFF = 0.3Fs for VBATT > 0.88 VDCIN

Input Capacitor Selection

The input capacitor must meet the ripple current

requirement (IRMS) imposed by the switching currents.

Nontantalum chemistries (ceramic, aluminum, or

OS-CON) are preferred due to their resilience to power-

up surge currents:



IRMS

=

ICHG





VBATT

(VDCIN

-

VBATT

)





VDCIN



The input capacitors should be sized so that the

temperature rise due to ripple current in continuous

conduction does not exceed approximately 10NC. The

maximum ripple current occurs at 50% duty factor or

VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the

application of interest does not achieve the maximum

value, size the input capacitors according to the worst-

case conditions.

Output Capacitor Selection

The output capacitor absorbs the inductor ripple current

and must tolerate the surge current delivered from the

battery when it is initially plugged into the charger.

As such, both capacitance and ESR are important

parameters in specifying the output capacitor as a filter

and to the ensure stability of the DC-DC converter. See the

Compensation section. Beyond the stability requirements,

it is often sufficient to make sure that the output capacitor’s

ESR is much lower than the battery’s ESR. Either tantalum

or ceramic capacitors can be used on the output.

Ceramic devices are preferable because of their good

voltage ratings and resilience to surge currents. For most

applications the output capacitance can be as low as

4.7FF. If the output voltage is low and the input voltage is

high, the output capacitance may need to be increased.

Applications Information

Layout and Bypassing

Bypass DCIN with a 0.1FF ceramic to ground (Figure 1).

N3 and Q1A protect the MAX17435/MAX17535 when the

DC power source input is reversed. Bypass VCC, DCIN,

LDO, and VAA, as shown in Figure 1.

Good PCB layout is required to achieve specified noise

immunity, efficiency, and stable performance. The

PCB layout artist must be given explicit instructions—

preferably, a sketch showing the placement of the power

switching components and high current routing. Refer

to the PCB layout in the MAX17435 and MAX17535

Evaluation Kits for examples. A ground plane is essential

for optimum performance. In most applications, the circuit

is located on a multilayer board, and full use of the four or

more copper layers is recommended. Use the top layer

for high current connections, the bottom layer for quiet

connections, and the inner layers for an uninterrupted

ground plane.

Use the following step-by-step guide:

1) Place the high-power connections first, with their

grounds adjacent:

U Minimize the current-sense resistor trace lengths,

and ensure accurate current sensing with Kelvin

connections.

U Minimize ground trace lengths in the high-current

paths.

U Minimize other trace lengths in the high-current

paths.

U Use > 5mm wide traces in the high-current paths.

U Connect C1 and C2 to high-side MOSFET (10mm

max length).

U Minimize the LX node (MOSFETs, rectifier cathode,

inductor (15mm max length). Keep LX on one side

of the PCB to reduce EMI radiation.

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