MAX17499AAUB 查看數據表（PDF） - Maxim Integrated

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MAX17499AAUB

Current-Mode PWM Controllers with Programmable Switching Frequency

Maxim Integrated 

Current-Mode PWM Controllers with

Programmable Switching Frequency

MAX17499/MAX17500 fig02

VCC

2V/div

VIN

5V/div

0V

100ms/div

Figure 2. VIN and VCC During Startup When Using the

MAX17500 in Bootstrapped Mode (Figure 1)

For the MAX17500, the voltage at IN is normally derived

from a tertiary winding of the transformer. However, at

startup there is no energy being delivered through the

transformer; hence, a special bootstrap sequence is

required. Figure 2 shows the voltages at VIN and VCC

during startup. Initially, both VIN and VCC are 0V. After

the line voltage is applied, C1 charges through the

startup resistor, R1, to an intermediate voltage. At this

point, the internal regulator begins charging C2 (see

Figure 1). Only 50μA of the current supplied through R1

is used by the MAX17500; the remaining input current

charges C1 and C2. The charging of C2 stops when

the VCC voltage reaches approximately 9.5V, while the

voltage across C1 continues rising until it reaches the

wake-up level of 21.6V. Once VIN exceeds the boot-

strap UVLO threshold, NDRV begins switching the

MOSFET and transfers energy to the secondary and

tertiary outputs. If the voltage on the tertiary output

builds to higher than 9.74V (the bootstrap UVLO lower

threshold), then startup has been accomplished and

sustained operation commences. If VIN drops below

9.74V before startup is complete, the device goes back

to low-current UVLO. In this case, increase the value of

C1 to store enough energy to allow for the voltage at

the tertiary winding to build up.

UVLO Flag (UFLG)

The devices have an open-drain undervoltage flag out-

put (UFLG). When used with an optocoupler, the UFLG

output can serve to sequence a secondary-side con-

troller. An internal 210μs delay occurs the instant the

voltage on UVLO/EN drops below 1.17V until NDRV

stops switching. This allows for the UFLG output to

change state before the devices shut down (Figure 3).

When the voltage at the UVLO/EN is above the thresh-

old, UFLG is high impedance. When UVLO/EN is below

the threshold, UFLG goes low. UFLG is not affected by

bootstrap UVLO (MAX17500).

VUVLO/EN

VUFLG

1.23V

(±1%)

LOW

VNDRV

SHUTDOWN

HIGH-Z

3μs

tEXTR

3ms

1.17V (typ)

0.6μs

NDRV SWITCHING

LOW

tEXTF

210μs

Figure 3. UVLO/EN and UFLG Operation Timing

SHUTDOWN

10 ______________________________________________________________________________________

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