MAX3681(1996) 查看數據表（PDF） - Maxim Integrated
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MAX3681 Datasheet PDF : 8 Pages
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+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
SCLK
SD
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SYNC
PCLK
PD3
D4-
D0
D5
PD2
D3-
D1
D6
PD1
D2-
D2
D7
PD0
D1-
D3
D8
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2. Functional Timing Diagram
SCLK
SD
tSCLK = 1 / fSCLK
tSU
tH
PCLK
PD0–PD3
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
tCLK-Q
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