MAX3690(1999) 查看數據表（PDF） - Maxim Integrated

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MAX3690
(Rev.:1999)

+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET 8:1 Serializer

with Clock Synthesis and TTL Inputs

______________________________________________________________Pin Description

PIN

1–8

9, 10, 17,

18, 19, 24,

25, 26,

31, 32

11

12, 13, 16,

21, 28, 29

14

15

20

22

23

27

30

NAME

PD0–PD7

GND

PCLKO

VCC

SD-

SD+

CKSET

FIL-

FIL+

RCLK

PCLKI

FUNCTION

TTL Parallel-Data Inputs. Data is clocked in on the PCLKI signal’s positive transition.

Ground

TTL Parallel-Clock Output. Use positive transition of PCLKO to clock the overhead management

circuit.

+3.3V Supply Voltage

Inverting PECL Serial-Data Output

Noninverting PECL Serial-Data Output

Reference Clock Rate Programming Pin.

CKSET = open: Reference clock rate = 77.76MHz

CKSET = 20kΩ to GND: Reference clock rate = 51.84MHz

CKSET = GND: Reference clock rate = 38.88MHz

Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC.

Filter Capacitor Input. Connect a 1µF capacitor between FIL- and VCC.

TTL Reference-Clock Input. Connect a crystal reference clock (77.76MHz, 51.84MHz or 38.88MHz) to

the RCLK input. The active edge is the positive transitioning edge.

TTL Parallel-Clock Input. Connect the incoming parallel-data-clock signal to the PCLKI input. The

active edge is the positive transitioning edge.

_______________Detailed Description

The MAX3690 serializer comprises an 8-bit parallel

input register, an 8-bit shift register, control and timing

logic, a PECL output buffer, TTL input/output buffers,

and a frequency-synthesizing PLL (consisting of a

phase/frequency detector, loop filter/amplifier, voltage-

controlled oscillator, and programmable prescaler).

This device converts 8-bit-wide, 77Mbps parallel data

to 622Mbps serial data (Figure 1).

The PLL synthesizes an internal 622MHz reference

used to clock the output shift register. This clock is

generated by locking onto the external crystal refer-

ence clock signal (RCLK) operating at either

77.76MHz, 51.84MHz, or 38.88MHz. The incoming par-

allel data is clocked into the MAX3690 on the rising

transition of the parallel-clock-input signal (PCLKI). The

control and timing logic ensure proper operation if the

parallel-input register is latched within a window of time

that is defined with respect to the parallel-clock-output

signal (PCLKO). PCLKO is the synthesized 622MHz

internal serial-clock signal divided by eight. Parallel-

clock output to parallel-clock-input delay (skew) must

be observed. Figure 2 shows the timing diagram.

PECL Outputs

The serial-data PECL outputs (SD+, SD-) require 50Ω

DC termination to (VCC - 2V). See the Alternative PECL-

Output Termination section.

4 _______________________________________________________________________________________

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