MAX3881 查看數據表（PDF） - Maxim Integrated

零件编号

产品描述 (功能)

生产厂家

MAX3881

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

50Ω termination (Figure 5). AC-coupling is also

required to maintain the input common-mode level.

Exposed-Pad Package

The exposed-pad (EP), 64-pin TQFP incorporates fea-

tures that provide a very low thermal-resistance path for

heat removal from the IC. The pad is electrical ground

on the MAX3881 and must be soldered to the circuit

board for proper thermal and electrical performance.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies, keep ground con-

nections short, and use multiple vias where possible.

Use controlled-impedance transmission lines to inter-

face with the MAX3881 high-speed inputs and outputs.

Power-supply decoupling should be placed as close to

VCC pins as possible. To reduce feedthrough, take

care to isolate the input signals from the output signals.

VCC

0.1µF 25Ω

SDI+

PECL

LEVELS

0.1µF

100Ω

25Ω

SDI-

50Ω 50Ω

MAX3881

Figure 5. Interfacing with PECL Input Levels

MAX3881

3.3V

PHADJ+ (PIN 5)

Chip Information

TRANSISTOR COUNT: 2231

PROCESS: BiPolar

PHADJ- (PIN 6)

Figure 4. Phase-Adjust Resistor-Divider

8 _______________________________________________________________________________________

Share Link: