MAX4717(2002) 查看數據表（PDF） - Maxim Integrated
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MAX4717 Datasheet PDF : 15 Pages
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4.5Ω/20Ω, 300MHz Bandwidth, Dual SPDT
Analog Switches in UCSP
MAX4717/
MAX4718
VGEN
RGEN NC_
OR NO_
GND
V+
V+
COM_
IN_
VIL TO VIH
Figure 4. Charge Injection
Test Circuits/Timing Diagrams (continued)
VOUT
CL
VOUT
IN
OFF
∆VOUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆VOUT)(CL)
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
+5V 10nF
0V OR V+ IN_
V+
VIN
COM1
NC1
MAX4717/
MAX4718
VOUT
50Ω
NO1*
GND
NETWORK
ANALYZER
50Ω
50Ω
MEAS
50Ω
REF
50Ω
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
OFF-ISOLATION = 20log
VOUT
VIN
ON-LOSS = 20log
VOUT
VIN
CROSSTALK = 20log
VOUT
VIN
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
CAPACITANCE
METER
f = 1MHz
10nF V+
V+
COM_
MAX4717/
MAX4718
IN
NC_ or
NO_
GND
VIL OR VIH
Figure 6. Channel Off/On-Capacitance
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