MAX4717 查看數據表（PDF） - Maxim Integrated

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MAX4717

4.5Ω/20Ω, 300MHz Bandwidth, Dual SPDT Analog Switches in UCSP

Maxim Integrated 

4.5Ω/20Ω, 300MHz Bandwidth, Dual SPDT

Analog Switches in UCSP

Test Circuits/Timing Diagrams (continued)

RS

IN+

RS

IN-

NC1 OR

NO1

MAX4717

COM1

NC2 OR

NO2

COM2

RISE TIME DELAY = |tINRISE - tOUTRISE|

FALL TIME DELAY = |tINFALL - tOUTFALL|

OUT+ RISE TIME TO FALL TIME MISMATCH = |tOUTFALL - tOUTRISE|

CL

OUT-

CL

IN1

IN2

VIL TO VIH

V+

VIN+

50%

0V

V+

VIN-

50%

0V

V+

VOUT+

50%

0V

V+

VOUT-

50%

0V

tSKEW

Figure 3. Output Signal Skew

tINFALL

90%

10%

tOUTFALL

90%

10%

tINRISE

90%

10%

tOUTRISE

90%

10%

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