MAX5426 查看數據表（PDF） - Maxim Integrated
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MAX5426 Datasheet PDF : 9 Pages
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Precision Resistor Network for
Programmable Instrumentation Amplifiers
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13, 14
NAME
VDD
GND
VSS
FB2
OUT2
OFFSET
INDIF-
INDIF+
OUT
OUT1
FB1
CM
D0, D1
FUNCTION
Positive Power Supply. Bypass VDD to GND with a 0.1µF capacitor.
Ground
Negative Power Supply. Bypass VSS to GND with a 0.1µF capacitor.
First Stage Positive Input Terminal Resistor. Connect to the inverting terminal of the second input buffer
(see Figure 1).
First Stage Positive Output Terminal Resistor. Connect to the output terminal of the second input buffer.
Second Stage Offset Terminal. Connect to a DC voltage to offset the output of the differential amplifier.
Second Stage Negative Input Terminal Resistor. Connect to the inverting input terminal of the
differential op amp.
Second Stage Positive Input Terminal Resistor. Connect to the noninverting input terminal of the
differential op amp.
Second Stage Output Terminal, Final Output Terminal
First Stage Negative Output Terminal of Resistor. Connect to the output terminal of the first input buffer.
First Stage Negative Input Terminal of Resistor. Connect to the inverting input terminal of the first input
buffer.
Common-Mode Voltage. CM is the input common-mode voltage of the instrumentation amplifier.
Typically varies ±1% of input common-mode voltage.
Digital Inputs. See Table 1.
Detailed Description
The MAX5426 is a precision resistor network with low
temperature drift and high accuracy that performs the
same function as a precision resistor array and CMOS
switches. Operationally, this device consists of fixed
resistors and digitally controlled variable resistors that
provide differential gains of 1, 2, 4, and 8 (see
Functional Diagram). The MAX5426 provides gains
accurate to 0.025% (MAX5426A), 0.09% (MAX5426B)
or 0.5% (MAX5426C).
The MAX5426 is ideal for programmable instrumenta-
tion amplifiers. An offset pin is available to apply a DC
offset voltage to the output of the differential amplifier.
Pin CM is the common-mode input voltage and can be
buffered and connected to the common-mode input of
the instrumentation amplifier (usually the shield of the
input cable to reduce the effects of cable capacitance
and leakage).
Digital Interface Operation
The MAX5426 features a simple two-bit parallel pro-
gramming interface. D1 and D0 program the gain set-
ting according to the Logic-Control Truth Table (see
Table 1). The digital interface is CMOS/TTL logic com-
patible.
Timing Diagram
Figure 3 shows the timing diagram of MAX5426 for two
cases. In case 1, the differential input changes are at
OUT1 and OUT2, while the voltage settling is observed
at FB1 and FB2. The settling time (tSETTLE) is defined
as the time for the output voltage (from the change in
the input) to reach (and stay) within 0.02% of its final
value.
In case 2, the differential inputs (OUT1 and OUT2) are
at constant voltages, while D1 and D0 are varied (for
example from 01 to 10) to make a change in the gain.
No op amps are used in these cases.
Table 1. Logic-Control Truth Table
DIGITAL INPUTS
D1
D0
0
0
0
1
1
0
1
1
GAIN
1
2
4
8
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