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MAX6397_ATA-T 查看數據表(PDF) - Maxim Integrated

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MAX6397_ATA-T Datasheet PDF : 18 Pages
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Overvoltage Protection Switch/Limiter
Controllers Operate Up to 72V
IN
THERMAL
PROTECTION
5V
SET
1.23V
UVLO
LINEAR
REGULATOR
10V
CHARGE
PUMP
GATE
OUT
SHDN
REG
MAX6397
POK
MAX6398
VPOK_TH
GND
MAX6397 ONLY
Figure 1. Functional Diagram
The MAX6397 integrates a high-input-voltage, low-qui-
escent-current linear regulator in addition to an over-
voltage protector circuit. The linear regulator remains
enabled at all times to power low-current “always-on”
applications (independent of the state of the external
MOSFET). The regulator is offered with several stan-
dard output voltage options (5V, 3.3V, 2.5V, or 1.8V).
An open-drain power-good output notifies the system if
the regulator output falls to 92.5% or 87.5% of its nomi-
nal voltage. The MAX6397’s REG output operates inde-
pendently of the SHDN logic input.
The MAX6397/MAX6398 include internal thermal-shut-
down protection, disabling the external MOSFET and
linear regulator if the chip reaches overtemperature
conditions.
Linear Regulator (MAX6397 Only)
The MAX6397 is available with 5.0V, 3.3V, 2.5V, and 1.8V
factory-set output voltages. Each regulator sources up to
100mA and includes a current limit of 230mA. The linear
regulator operates in an always-on condition regardless
of the SHDN logic. For fully specified operation, VIN must
be greater than 6.5V for the MAX6397L/M (5V regulator
output). The actual output current may be limited by the
operating condition and package power dissipation.
Power-OK Output
POK is an open-drain output that goes low when REG
falls to 92.5% or 87.5% (see the Selector Guide) of its
nominal output voltage. To obtain a logic-level output,
connect a pullup resistor from POK to REG or another
system voltage. Use a resistor in the 100krange to
minimize current consumption. POK provides a valid
logic-output level down to VIN = 1.5V.
GATE Voltage
The MAX6397/MAX6398 use a high-efficiency charge
pump to generate the GATE voltage. Upon VIN exceed-
ing the 5V (typ) UVLO threshold, GATE enhances 10V
above IN (for VIN 14V) with a 75µA pullup current. An
overvoltage condition occurs when the voltage at SET
pulls above its 1.215V threshold. When the threshold is
crossed, GATE falls to OUT within 100ns with a 100mA
(typ) pulldown current. The MAX6397/MAX6398 include
an internal clamp to OUT that ensures GATE is limited
to 18V (max) above OUT to prevent gate-to-source
damage to the external FET.
The GATE cycle during overvoltage limit and overvolt-
age switch modes are quite similar but have distinct
characteristics. In overvoltage switch mode (Figure 2a),
GATE is enhanced to VIN + 10V while the monitored IN
voltage remains below the overvoltage fault threshold
(SET < 1.215V). When an overvoltage fault occurs (SET
1.215V), GATE is pulled one diode below OUT, turn-
ing off the external FET and disconnecting the load
from the input. GATE remains low (FET off) as long as
VIN is above the overvoltage fault threshold. As VIN falls
back below the overvoltage fault threshold (-5% hys-
teresis) GATE is again enhanced to VIN + 10V.
In overvoltage limit mode (Figure 2b), GATE is enhanced
to VIN + 10V. While the monitored OUT voltage remains
below the overvoltage fault threshold (SET < 1.215V).
When an overvoltage fault occurs (SET 1.215V),
GATE is pulled low one diode drop below OUT until
OUT drops 5% below the overvoltage fault threshold.
GATE is then turned back on until OUT again reaches
the overvoltage fault threshold and GATE is again
turned off.
8 _______________________________________________________________________________________

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