MAX7032 查看數據表（PDF） - Maxim Integrated

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MAX7032

Low-Cost, Crystal-Based, Programmable, ASK/FSK Transceiver with Fractional-N PLL

Maxim Integrated 

Low-Cost, Crystal-Based, Programmable,

ASK/FSK Transceiver with Fractional-N PLL

Table 3. Register Summary

REGISTER A[5:0]

0x00

REGISTER NAME

Power configuration

DESCRIPTION

Enables/disables the LNA, AGC, mixer, baseband, peak

detectors, PA, and RSSI output (see Table 5).

0x01

Control

Controls AGC lock, gain state, peak-detector tracking, polling

timer and FSK calibration, clock signal output, and sleep mode

(see Table 6).

0x02

Configuration0

Sets options for modulation, TX/RX mode, manual-gain mode,

discontinuous receive mode, off-timer and on-timer prescalers

(see Table 7).

0x03

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x1A

Configuration1

Oscillator frequency

Off timer—tOFF (upper byte)

Off timer—tOFF (lower byte)

CPU recovery timer—tCPU

RF settling timer—tRF (upper

byte)

RF settling timer—tRF (lower

byte)

On timer—tON (upper byte)

On timer—tON (lower byte)

Transmitter low-frequency

setting—TxLOW (upper byte)

Transmitter low-frequency

setting—TxLOW (lower byte)

Transmitter high-frequency

setting—TxHIGH (upper byte)

Transmitter high-frequency

setting—TxHIGH (lower byte)

Status register (read only)

Sets options for automatic FSK calibration, clock output, output

clock divider ratio, AGC dwell timer (see Tables 8, 10, 11, and 12).

Sets the internal clock frequency divisor. This register must be set

to the integer result of fXTAL/100kHz (see the Oscillator Frequency

Register (Address 0x05) section).

Sets the duration that the MAX7032 remains in low-power mode

when DRX is active (see Table 12).

Increases maximum time the MAX7032 stays in lower power mode

while CPU wakes up when DRX is active (see Table 13).

During the time set by the RF settling timer, the MAX7032 is

powered on with the peak detectors and the data outputs disabled

to allow time for the RF section to settle. DIO must be driven low at

any time during tLOW = tCPU + tRF + tON or the timer sequence

restarts (see Table 14).

Sets the duration that the MAX7032 remains in active mode when

DRX is active (see Table 15).

Sets the low frequency (FSK) of the transmitter or the carrier

frequency of ASK for the fractional-N synthesizer.

Sets the high frequency (FSK) of the transmitter for the fractional-N

synthesizer.

Provides status for PLL lock, AGC state, crystal operation, polling

timer, and FSK calibration (see Table 9).

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