MAX7033EUI(2011) 查看數據表（PDF） - Maxim Integrated
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MAX7033EUI Datasheet PDF : 16 Pages
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315MHz/433MHz ASK Superheterodyne
Receiver with AGC Lock
Pin Description
PIN
TSSOP THIN QFN
NAME
FUNCTION
1
29
XTAL1 Crystal Input 1 (See the Phase-Locked Loop section)
Positive Analog Supply Voltage. For +5V operation, pin 2 is the output of an on-chip +3.2V
low-dropout regulator, and should be bypassed to AGND with a 0.1μF capacitor as close as
2, 7
4, 30
AVDD possible to the pin. Pin 7 must be externally connected to the supply from pin 2, and bypassed
to AGND with a 0.01μF capacitor as close as possible to the pin. (See the Voltage Regulator
section and the Typical Application Circuit.)
3
31
LNAIN Low-Noise Amplifier Input (See the Low-Noise Amplifier section)
4
5, 10
32
LNASRC Low-Noise Amplifier Source for External Inductive Degeneration. Connect inductor to ground
to set the LNA input impedance (See the Low-Noise Amplifier section).
2, 7
AGND Analog Ground
6
3
LNAOUT
Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter (See the Low-
Noise Amplifier section).
8
5
MIXIN1 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT.
9
6
MIXIN2 2nd Differential Mixer Input. Connect through a 100pF capacitor to VDD3 side of the LC tank.
Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL
11
8
IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = VDD5 to center image
rejection at 433MHz.
12
9
MIXOUT 330Ω Mixer Output. Connect to the input of the 10.7MHz bandpass filter.
13
10
DGND Digital Ground
14
11
DVDD Positive Digital Supply Voltage. Connect to both of the AVDD pins. Bypass to DGND with a
0.01μF capacitor as close as possible to the pin. (See the Typical Application Circuit.)
15
12
AC Automatic Gain Control. See Figure 1. Internally pulled down to AGND with a 100kΩ resistor.
16
14
XTALSEL
Crystal Divider Ratio Select. Drive XTALSEL low to select fLO/fXTAL ratio of 64, or drive
XTALSEL high to select fLO/fXTAL ratio of 32.
17
15
IFIN1 1st Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF
capacitor as close to the pin as possible.
18
16
IFIN2
2nd Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a
10.7MHz bandpass filter.
19
17
DFO Data Filter Output
20
18
DSN Negative Data Slicer Input
21
19
OPP Noninverting Op-Amp Input for the Sallen-Key Data Filter
22
20
DFFB Data-Filter Feedback Node. Input for the feedback of the Sallen-Key data filter.
23
22
DSP Positive Data Slicer Input
+5V Supply Voltage. Bypass to AGND with a 0.01μF capacitor as close as possible to the pin.
24
23
VDD5
For +5V operation, VDD5 is the input to an on-chip voltage regulator whose +3.2V output
appears at the pin 2 AVDD pin. (See the Voltage Regulator section and the Typical Application
Circuit.)
25
24
DATAOUT Digital Baseband Data Output
26
26
PDOUT Peak-Detector Output
27
27
SHDN Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with
a 100kΩ resistor.
8 _______________________________________________________________________________________
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