MAX8643AETG(2007) 查看數據表（PDF） - Maxim Integrated

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MAX8643AETG
(Rev.:2007)

3A, 2MHz Step-Down Regulator with Integrated Switches

Maxim Integrated 

3A, 2MHz Step-Down Regulator

with Integrated Switches

COMPENSATION

TRANSFER

FUNCTION

DOUBLE POLE

OPEN-LOOP

GAIN

THIRD

POLE

GAIN (dB)

POWER-STAGE

TRANSFER

FUNCTION

SECOND

POLE

FIRST AND SECOND ZEROS

Figure 4. Type III Compensation Illustration

fZ1_EA

=

2π

x

1

R1

x

C1

fP3 _EA

=

2π

x

1

R1 x

C2

fP2 _EA

=

2π

1

x R2

x C3

The above equations are based on the assumptions that

C1>>C2, and R3>>R2, which are true in most applica-

tions. Placements of these poles and zeros are deter-

mined by the frequencies of the double pole and ESR

zero of the power transfer function. It is also a function

of the desired closed-loop bandwidth. The following

section outlines the step-by-step design procedure to

calculate the required compensation components for

the MAX8643A. When the output voltage of the

MAX8643A is programmed to a preset voltage, R3 is

internal to the IC and R4 does not exist (Figure 3b).

When externally programming the MAX8643A (Figure

3a), the output voltage is determined by:

R4

=

0.6 × R3

(VOUT − 0.6)

The zero-cross frequency of the closed-loop, fC, should

be between 10% and 20% of the switching frequency,

fS. A higher zero-cross frequency results in faster tran-

sient response. Once fC is chosen, C1 is calculated

from the following equation:

C1

=

2

x

π

x

2.5 VIN

R3 x (1+

RL

RO

)

×

fC

Due to the underdamped nature of the output LC dou-

ble pole, set the two zero frequencies of the type III

compensation less than the LC double-pole frequency

to provide adequate phase boost. Set the two zero fre-

quencies to 80% of the LC double-pole frequency.

Hence:

R1 = 1 x L x CO x (RO + ESR)

0.8 x C1

RL + RO

C3 = 1 x L x CO x (RO + ESR)

0.8 x R3

RL + RO

Setting the second compensation pole, fP2_EA, at

fZ_ESR yields:

R2 = CO x ESR

C3

Set the third compensation pole at 1/2 of the switching

frequency to gain some phase margin. Calculate C2 as

follows:

C2 =

1

π x R1 x fS × 2

The above equations provide accurate compensation

when the zero-cross frequency is significantly higher

than the double-pole frequency. When the zero-cross

frequency is near the double-pole frequency, the actual

zero-cross frequency is higher than the calculated fre-

quency. In this case, lowering the value of R1 reduces

the zero-cross frequency. Also, set the third pole of the

type III compensation close to the switching frequency

if the zero-cross frequency is above 200kHz to boost

the phase margin. The recommended range for R3 is

2kΩ to 10kΩ. Note that the loop compensation remains

unchanged if only R4’s resistance is altered to set dif-

ferent outputs.

Soft-Starting into a Prebiased Output

When the PREBIAS pin is left unconnected, the

MAX8643A is capable of soft-starting up into a prebiased

output without discharging the output capacitor. This

type of operation is also termed monotonic startup.

However, in order to avoid output voltage glitches during

soft-start, it should be ensured that the inductor current

is in continuous conduction mode during the end of the

soft-start period. This is done by satisfying the following

equation:

CO

×

VO

tSS

≥

IP−P

2

______________________________________________________________________________________ 13

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