MCRF450 查看數據表（PDF） - Microchip Technology

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MCRF450

13.56 MHz Read/Write Passive RFID Device

Microchip Technology 

MCRF450/451/452/455

4.0 ANALOG FRONT-END

This section includes high and low voltage regulators,

Power-on Reset, 70 kHz clock generator and

modulation circuits.

4.1 High and Low Voltage Regulator

The high voltage circuit generates the programming

voltage for the memory section. The low voltage circuit

generates DC voltage (VDD) to operate the device.

4.2 Power-On Reset (POR)

This circuit generates a Power-on Reset (POR)

voltage. The POR releases when sufficient power has

been developed by the voltage regulator to allow for

correct operation.

4.3 Clock Generator

This circuit generates a clock (CLK). The main clock is

generated by an on-board 70 kHz time base oscillator.

This clock is used for all timing in the device, except for

the Fast mode PPM decoding.

4.4 Data Modulation

The data modulation circuit consists of a modulation

transistor and a LC resonant circuit. The resonant

circuit must be tuned to the carrier frequency of the

Interrogator (i.e., 13.56 MHz) for maximum

performance.

The modulation transistor is placed between antenna B

and VSS pads. It is designed to result in the turn-on

resistance of less than five ohms (RM). This small turn-

on resistance shorts the resonant circuit component

between antenna B and VSS pads as it turns on. This

results in a change of the resonant frequency of the

resonant circuit. Consequently, the resonant circuit

becomes detuned with respect to the carrier frequency

of the Interrogator. The voltage across the resonant

circuit is minimized during this time. This condition is

called “cloaking”.

The transistor, however, releases the resonant circuit

as it turns off. Therefore, the resonant circuit tunes to

the carrier frequency of the Interrogator again and

develops maximum voltage. This condition is called

“uncloaking”.

The device transmits data by cloaking and uncloaking,

based on the on/off condition of the modulation transis-

tor. Using the 70 kHz Manchester format, the data bit

‘0’ will be sent by cloaking and uncloaking the device

for 7 µs each. Similarly, the data bit ‘1’ will be sent by

uncloaking and cloaking the device for 7 µs each. See

Figure 6-1 for the Manchester waveform.

4.5 Detuning Circuit

The purpose of this circuit is to prevent excessive RF

voltage across the resonant circuit.

This circuit monitors VDD and detunes the resonant

circuit if the RF coil voltage exceeds the threshold limit

(VDETUNE), which is above the operating voltage of the

device.

DS40232H-page 14

 2003 Microchip Technology Inc.

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