MPC9600FA 查看數據表（PDF） - Motorola => Freescale

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MPC9600FA

Low Voltage 2.5V and 3.3V CMOS PLL Clock Driver

Motorola => Freescale 

Freescale Semiconductor, Inc.

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50Ω resistance to VCC÷2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each

output of the MPC9600 clock driver. For the series

terminated case however there is no DC current draw, thus

the outputs can drive multiple series terminated lines.

Figure 8. “Single versus Dual Transmission Lines” illustrates

an output driving a single series terminated line versus two

series terminated lines in parallel. When taken to its extreme

the fanout of the MPC9600 clock driver is effectively doubled

due to its capability to drive multiple lines.

MPC9600

OUTPUT

BUFFER

IN

14Ω

RS = 36 Ω ZO = 50 Ω

OutA

MPC9600

OUTPUT

BUFFER

IN

14Ω

RS = 36 Ω ZO = 50 Ω

RS = 36 Ω ZO = 50 Ω

OutB0

OutB1

Figure 8. Single versus Dual Transmission Lines

The waveform plots in Figure 9. “Single versus Dual Line

Termination Waveforms” show the simulation results of an

output driving a single line versus two lines. In both cases the

drive capability of the MPC9600 output buffer is more than

sufficient to drive 50 Ω transmission lines on the incident

edge. Note from the delay measurements in the simulations a

delta of only 43 ps exists between the two differently loaded

outputs. This suggests that the dual line driving need not be

used exclusively to maintain the tight output-to-output skew

of the MPC9600. The output waveform in Figure 9. “Single

versus Dual Line Termination Waveforms” shows a step in

the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel

combination of the 36Ω series resistor plus the output

impedance does not match the parallel combination of the

line impedances. The voltage wave launched down the two

lines will equal:

VL = VS ( Z0 ÷ (RS+R0 +Z0))

Z0 = 50 Ω || 50 Ω

RS = 36 Ω || 36 Ω

R0 = 14 Ω

VL = 3.0 ( 25 ÷ (18+17+25)

= 1.31 V

At the load end the voltage will double due to the near unity

reflection coefficient, to 2.6 V. It will then increment towards

the quiescent 3.0 V in steps separated by one round trip

delay (in this case 4.0 ns).

3.0

OutA

2.5

tD = 3.8956

OutB

tD = 3.9386

2.0

In

1.5

1.0

0.5

0

2

4

6

8

10 12 14

TIME (nS)

Figure 9. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 10. “Optimized Dual Line Termination”

should be used. In this case the series terminating resistors

are reduced such that when the parallel combination is added

to the output buffer impedance the line impedance is

perfectly matched.

MPC9600

OUTPUT

BUFFER

RS = 22 Ω ZO = 50 Ω

14Ω

RS = 22 Ω ZO = 50 Ω

14 Ω + 22 Ω k 22 Ω = 50 Ω k 50 Ω

25 Ω = 25 Ω

Figure 10. Optimized Dual Line Termination

MOTOROLA

For More Informa1t0ion On This Product,

Go to: www.freescale.com

TIMING SOLUTIONS

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