MX88L284AEC 查看數據表（PDF） - Unspecified

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MX88L284AEC

Highly integration chip for Flat Panel Display application

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MX88L284AEC

Revision: 1.06A

Table of Contents

GENERAL DESCRIPTION ...................................................................................................................................4

APPLICATIONS .....................................................................................................................................................4

FEATURES .............................................................................................................................................................4

GENERAL FEATURES ...............................................................................................................................................4

INPUT.....................................................................................................................................................................5

OUTPUT .................................................................................................................................................................5

CPU INTERFACE.....................................................................................................................................................6

MEMORY INTERFACE ..............................................................................................................................................6

POWER ................................................................................................................................................................... 6

OTHERS .................................................................................................................................................................6

CHIP BLOCK DIAGRAM .....................................................................................................................................7

SYSTEM BLOCK DIAGRAM FOR LCD MONITOR (TTL AND PANELLINK/LVDS INTERFACED)........7

SYSTEM DIAGRAM W/O FRAME BUFFER......................................................................................................8

SYSTEM DIAGRAM FOR DIGITAL INPUT INTERFACE ...............................................................................8

PIN CONFIGURATIONS.......................................................................................................................................9

GENERAL DESCRIPTION .................................................................................................................................10

VIP (VIDEO INPUT PROCESSOR) FUNCTION DESCRIPTION.......................................................................................10

MIU (MEMORY INTERFACE UNIT) FUNCTIONAL DESCRIPTION ...............................................................................10

MEMORY CONFIGURATION TABLE.........................................................................................................................11

VOP (VIDEO OUTPUT PROCESSOR) FUNCTION DESCRIPTION ..................................................................................11

BIU (BUS INTERFACE UNIT) FUNCTION DESCRIPTION ............................................................................................11

PIN DESCRIPTION..............................................................................................................................................12

CPU INTERFACE PINS: (15 PINS) ...........................................................................................................................12

DRAM INTERFACE PINS: (52 PINS) ** 3.3 VOLT INTERFACE *** ..........................................................................12

INPUT INTERFACE PINS: (30 PINS)..........................................................................................................................13

LCD INTERFACE PINS: (53 PINS) ...........................................................................................................................13

OSD INTERFACE PINS: (6 PINS) .............................................................................................................................14

INTERNAL VCG INTERFACE PINS: (2 PINS) ............................................................................................................14

OTHER INTERFACE PINS: (9 PINS) ..........................................................................................................................14

EXTERNAL CLOCK INPUT INTERFACE PINS: (2) .....................................................................................................15

POWER PINS: ........................................................................................................................................................15

AC CHARACTERISTICS ....................................................................................................................................16

AC TIMINGS IF THE LOAD OF ALL OUTPUT PINS IS 5~20PF........................................................................................16

1.

INPUT SIGNAL........................................................................................................................................16

2. OUTPUT SIGNAL................................................................................................................................................19

EXTERNAL OSD SIGNAL .......................................................................................................................................20

3. DIRECT CPU INTERFACE...................................................................................................................................21

4. SERIAL BUS INTERFACE.....................................................................................................................................22

5. FRAME MEMORY (SDRAM/SGRAM) INTERFACE ..............................................................................................23

6. EXTERNAL CLOCK INPUT INTERFACE .................................................................................................................25

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