MX88L284AEC 查看數據表（PDF） - Unspecified

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MX88L284AEC

Highly integration chip for Flat Panel Display application

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MX88L284AEC

Revision: 1.06A

General Description

There are four major parts in this chip which include VIP (Video Input Processor), MIU (Memory

Interface Unit), VOP (Video Output Processor) and BIU (CPU Bus Interface Unit). Following is the block

and description of these parts.

SDRAM or

SGRAM

PC (RGB)/

VIP

Video (YUV)

VIP LB

MIU

BIU

VOP LB

VOP

FPD

Panel

8/16 bit uP

OSD

GENERATOR

Fig. 1 Chip Level Block Diagram

VIP (Video Input Processor) Function Description

VIP is a Video Input Process unit which processes incoming data either from Graphic card or Video

Decoder.

With Line Buffers and Decimation logic based on proprietary SmartscalingTM –2 algorithm , it can process

input data and then write to frame buffer . Furthermore, it can detect the polarity of input H/V SYNC and

then do the normalization of them and also detect the ODD/EVEN field of the input interlaced data. It can

also measure the pulse width and period of input H/V SYNC for system application purposes.

Video encoder interface is supported for video image input.

MIU (Memory Interface Unit) Functional Description

MIU is a interface unit between external DRAM and this chip. We support 6 kinds of configurations for

SDRAM and SGRAM through POWER_ON Strapped_Input or register defined value.

DRAM Configuration (Support 8M SGRAM and 16M SDRAM)

DRAM Type

SGRAM

SGRAM

SDRAM

SDRAM

DRAM Number

1

2

1

2

Bus Width

32 bits

32 bits

16 bits

32 bits

10

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