OR2C04A 查看數據表（PDF） - Lattice Semiconductor
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OR2C04A Datasheet PDF : 192 Pages
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ORCA Series 2 FPGAs
Programmable Input/Output Cells (continued)
Data Sheet
January 2002
PA
PB
PC
PD
DT
DT
DT
DT
PIC DETAIL
K
J
PXL[1]
A PXL[0]
PXH[0]
PXH[1]
B PXH[2]
PXH[3]
PX2[2]
PX2[3]
C PX2[0]
PX2[1]
M
PX1[0]
PX1[1]
D PX1[2]
PX1[3]
N
O
I
L
F
Q
PXL[0]
PXL[1]
A
PXH[0]
PXH[1]
PXH[2]
B
PXH[3]
P
PX2[0]
PX2[1]
PX2[2]
C
PX2[3]
C
M
PX1[0]
PX1[1]
PX1[2]
D
PX1[3]
D
N
O
P
LLDRV
P
Q
F
E
G
Figure 26. PIC Architecture
5-2843(F).r8
PLC-PIC Routing Resources
There is no direct connection between the inter-PIC
lines and the PLC lines. All connections to/from the
PLC must be done through the connecting lines which
are perpendicular to the lines in the PIC. The use of
perpendicular and parallel lines will be clearer if the
PLC and PIC architectures (Figure 23 and Figure 26)
are placed side by side. Twenty-nine lines in the PLC
can be connected to the 15 lines in the PIC.
Multiple connections between the PIC PX1 lines and
the PLC X1 lines are available. These allow buses
placed in any arbitrary order on the I/O pads to be
unscrambled when placed on the PLC X1 lines. Con-
nections are also available between the PIC PX2 lines
and the PLC X1 lines.
There are eight tridirectional (four TRIDI/four TRIDIH)
buffers in each PIC; they can do the following:
■ Drive a signal from an I/O pad onto one of the adja-
cent PLC’s XL or XH lines
■ Drive a signal from an I/O pad onto one of the two
PXL or four PXH lines in the PIC
■ Drive a signal from the PLC XL or XH lines onto one
of the two PXL or four PXH lines in the PIC
■ Drive a signal from the PIC PXL or PXH lines onto
one of the PLC XL or XH lines
30
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