PEB20320 查看數據表（PDF） - Infineon Technologies

零件编号

产品描述 (功能)

生产厂家

PEB20320

Multichannel Network Interface Controller for HDLC

Infineon Technologies 

PEB 20320

1.3 Pin Definitions and Functions

Introduction

Pin Definitions and Functions

Pin No.

Symbol

P-MQFP-160-1

Input (I) Function

Output (O)

83, 87, 88, 92, VSS

97, 103, 104,

110, 111, 117,

123, 130, 136,

141, 144, 150,

151, 157, 3, 9,

10, 16, 22, 23,

29, 30, 36, 59,

62, 64, 77

I

Ground (0 V)

All pins must have the same level.

73

I/M

I

Intel Bus Mode or Motorola Bus Mode

By connecting this pin to either VSS or VDD

the bus interface can be adapted to either

Intel or Motorola environment. The data is

interpreted either in Intel or Motorola

manner; i.e. little or big endian convention.

I/M = low: Intel bus mode

I/M = high: Motorola bus mode

39

A31

O

Address Bit 31

(Intel non-parity/Motorola) tristate when

unused.

DP3

I/O Data Parity 3 (Intel parity mode),

bidirectional tristate line containing/

expecting parity bit of D(31:24).

35

A30

O

Address Bit 30

(Intel non-parity/Motorola) tristate when

unused.

DP2

I/O Data Parity 2 (Intel parity mode),

bidirectional tristate line containing/

expecting parity bit of D(23:16).

Note: Input pins that are unused in a specific configuration must be strapped to VSS.

I/O or output pins that are unused in a specific configuration must be left open!

User’s Manual

12

01.2000

Share Link: