DAC16GS 查看數據表（PDF） - Analog Devices

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DAC16GS

16-Bit High Speed Current-Output DAC

Analog Devices 

DAC16

+5V

10k⍀

1

2

3

4

5

6

7

8

9

10

11

12

24 NC

23

22

21

20

19

18

17

16

15

14

13

–15V

Figure 2. Burn-In Diagram

OPERATION

Novel DAC Architecture

The DAC16 was designed with a compound DAC architecture

to achieve high accuracy, excellent linearity, and low transition

errors. As shown in Figure 3, the DAC’s five most-significant

bits utilize 31 identical segmented current sources to obtain

optimal high speed settling at major code transitions. The lower

nine bits utilize an inverted R-2R ladder network which is laser-

trimmed to ensure excellent differential nonlinearity. The middle

two bits (DB9 and DB10) arc binary-weighted and scaled from

the MSB segments. Note that the flow of output current is into

the DAC16—there is no signal inversion. As shown, the switches

for each current source are essentially diodes. It is for this rea-

son that the output voltage compliance of the DAC16 is limited

to a few millivolts. The DAC16 was designed to operate with an

operational amplifier configured as an I–V converter; therefore,

the DAC16’s output must be connected to the sum node of an

operational amplifier for proper operation. Exceeding the output

voltage compliance of the DAC16 will introduce linearity errors.

The reference current buffer assures full accuracy and fast set-

tling by controlling the MSB reference node. The 16-bit paral-

lel digital input is TTL/CMOS compatible and unbuffered,

minimizing the deleterious effects of digital feedthrough

while allowing the user to tailor the digital interface to

the speed requirements and bus configuration of the

application.

Equivalent Circuit Analysis

An equivalent circuit for static operation of the DAC16 is

illustrated in Figure 4. IREF is the current applied to the

DAC16 and is set externally to the device by VREF and

RREF. The output capacitance of the DAC16 is approxi-

mately 10 pF and is code independent. Its output resis-

tance RO is code dependent and is given by:

1

RO

=

1

8 kΩ

+

DB 9

288 kΩ

+

DB10

144 kΩ

+

X

72 kΩ

where

DB9 = State of Data Bit 9 = 0 or 1;

DB10 = State of Data Bit 10 = 0 or 1; and

X = Decimal representation of the 5 MSBs (DB11–DB15)

= 0 to 31.

IDAC

RO

IOUT

CO

65,535 Digital Code

IOUT = 8 • IREF

65,536

RO = SEE TEXT

CO = 10pF

Figure 4. Equivalent Circuit for the DAC16

Table I provides the relationship between the input digital

code and the output resistance of the DAC16.

Table I. DAC16 Output Resistance vs. Digital Code

Hex Digital Code

FFFF

BFFF

7FFF

3FFF

0

Scale

Zero

1/4

1/2

3/4

Full – 1 LSB

Output Resistance

8 kΩ

4.2 kΩ

2.9 kΩ

2.2 kΩ

1.8 kΩ

IOUT

DB0 – DB8

AGND

DB11 – DB15

DB10 DB9

8k⍀ 8k⍀

4k⍀

4k⍀ 4k⍀ 4k⍀

4k⍀

DB0 – DB15

SWITCH DETAIL

IREF

18k⍀

SW SW

SW SW

SW10 SW9

SW8 SW7 SW6

SW0

+5V

31 CURRENT SOURCES

125␮A EACH

62.5␮A 31.25␮A

9 CURRENT SOURCES

15.63␮A EACH

FROM

SWITCH

DECODER

CCOMP

Figure 3. DAC16 Architecture

–4–

REV. B

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