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SAB83C166W-5M 查看數據表(PDF) - Infineon Technologies

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SAB83C166W-5M Datasheet PDF : 67 Pages
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SAB 80C166W/83C166W
AC Characteristics (cont’d)
Multiplexed Bus
VCC = 5 V ± 10 %; VSS = 0 V
TA = 0 to + 70 ˚C for SAB 83C166W-5M, SAB 80C166W/83C166W-M
TA = – 40 to + 85 ˚C for SAB 83C166W-5M-T3, SAB 80C166W/83C166W-M-T3
TA = – 40 to +110 ˚C for SAB 83C166W-5M-T4, SAB 80C166W/83C166W-M-T4
CL (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
ALE cycle time = 6 TCL (150 ns at 20-MHz CPU clock)
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
RD, WR low time
(with RW-delay)
RD WR low time
(no RW-delay)
RD to valid data in
(with RW-delay)
RD to valid data in
(no RW-delay)
ALE low to valid data in
Address to valid data in
Data hold after RD
rising edge
Symbol CPU Clock = 16 MHz Variable CPU Clock
Duty cycle 0.4 to 0.6
1/TCLP = 1 to 20 MHz
min.
max.
min.
max.
t5 CC 15 + tA
t6 CC 10 + tA
t7 CC 15 + tA
t8 CC 15 + tA
t9 CC -10 + tA
TCLmin - 10 –
+ tA
TCLmin - 15
+ tA
TCLmin - 10
+ tA
TCLmin - 10
+ tA
-10 + tA
Unit
ns
ns
ns
ns
ns
t10 CC –
5
5
ns
t11 CC –
42.5
TCLmax + 5
ns
t12 CC 52.5 + tC
t13 CC 77.5 + tC
t14 SR –
t15 SR –
t16 SR –
t17 SR –
t18 SR 0
47.5 + tC
72.5 + tC
72.5
+ tA + tC
100
+ 2tA + tC
TCLP - 10
ns
+ tC
TCLP + TCLmin
ns
- 10 + tC
TCLP - 20
ns
+ tC
TCLP + TCLmin ns
- 20 + tC
TCLP + TCLmin ns
- 20 + tC
2TCLP - 25
ns
+ 2tA + tC
0
ns
Semiconductor Group
51

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